cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 153

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
28229-DSH-001-D
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0x27—IDLMSK4 (Receive Idle Cell Mask Control Register 4)
0x28—ENCELLT (Transmit Cell Interrupt Control Register)
IdlMsk4[7]
IdlMsk4[6]
IdlMsk4[5]
IdlMsk4[4]
IdlMsk4[3]
IdlMsk4[2]
IdlMsk4[1]
IdlMsk4[0]
EnParErrInt
EnSOCErrInt
EnTxOvflInt
EnRxOvflInt
EnCellSentInt
The IDLMSK4 register contains the fourth byte of the Receive Idle Cell Mask. (See
0x24—RXMSKL1.)
The ENCELLT register controls which of the interrupts listed in the TxCellInt
register (0x2C) appear on the MicroInt* pin (pin T1), provided that both EnTxCellInt
(bit 1) in the ENSUMINT register (0x01) and EnPortInt in the ENSUMPORT register
(0x0201) for this port are enabled, and EnIntPin (bit 3) in the MODE register
(0x0202) is enabled.
Name
Name
—
—
—
Mindspeed Technologies
These bits hold the Receive Idle cell header mask for Octet 4 of the incoming cell.
When written to a logical 1, this bit enables the Parity Error Interrupt.
When written to a logical 1, this bit enables the Start of Cell Error Interrupt.
When written to a logical 1, this bit enables the Transmit FIFO Overflow Interrupt.
When written to a logical 1, this bit enables the Receive FIFO Overflow Interrupt.
When written to a logical 1, this bit enables the Cell Sent Interrupt.
Reserved for factory test, ignore.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Description
Description
™
Registers
7
-
53