cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 20

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

Introduction to IMA
Table 1-1. IMA Overhead Cell Definition (2 of 3)
1-6
Octet
10
11
12
13
14
Link Stuff Indication (LSI) Stuff Indication code for link on which ICP cell is being sent
Status / Control Change
Group Status & Control
Indication (SCCI)
Transmit Timing
Information
IMA ID
Field
Bits 7–3 Unused and set to 0
Bits 2–0 111: no imminent stuff (default)
Status and Control Change Indication: 0 to 255 and cycling (count to be incremented every
time there is a change to octets 12 to 49).
Logical IMA group ID
Bits 7–4 Group Status
Bits 3–2 Others: Reserved
Symmetry of Group
Bits 1–0 11: Reserved
IMA Frame Length
Transmit Clock Information
100: stuff event in 4 ICP cell locations (optional)
011: stuff event in 3 ICP cell locations (optional)
010: stuff event in 2 ICP cell locations (optional)
001: stuff event at the next ICP cell location (mandatory)
000: This is one out of the 2 ICP cells comprising the stuff event (mandatory)
0000: Start-up
0001: Start-up-Ack
0010: Config-Aborted: Unsupported M
0011: Config-Aborted: Incompatible Symmetry
0100: Config-Aborted: Unsupported IMA version
01xx: Available for other Config Abort reasons
1000: Insufficient-Links
1001: Blocked
1010: Operational
00: Symmetrical configuration and operation
01: Symmetrical configuration and asymmetric operation
10: Asymmetrical configuration and operation
00: M=32
01: M=64
10: M=128
11: M=256
Bits 7–6 Unused, set to 00
Bit 5 Transmit Clock Mode (0: ITC mode, 1: CTC mode)
Bits 4–0 Tx LID of the timing reference link (TRL)—Range: 0 to 31
Mindspeed Technologies
Description
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CX28224/5/9 Data Sheet
28229-DSH-001-D