cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 171

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
28229-DSH-001-D
6–4
3–0
7–0
4–0
Bit
Bit
Bit
7
7
6
5
Default
Default
Default
0x00
0x00
—
—
—
0
0
0
0x407—IMA_MEM_TEST_CTL (IMA Memory Test Control / Address MSBs)
0x408—IMA_MEM_TEST_DATA (IMA Memory Test Data)
0x409—IMA_LNK_DIAG_CTL (IMA Link Diagnostic Control Register)
Memory Test
Address Bit 20
RAM Test Access
Memory Test
Address Bits 19–16
Memory Test Data
Link Delay Write
Counter
Link Diagnostic PHY
Address
This register is used to specify a port number for observation of link differential delay
and anomalies. The contents of this register are used to report the link information via
registers 0x409–0x40B. Bit 5 of this register is read-only.
Name
Name
Name
—
—
Mindspeed Technologies
This field contains the most significant bit of the memory test address for the
selected memory component.
0 = no test selected, normal operation
1 = SRAM Test
2–7 = Reserved
This field contains the most significant bits of the memory test address for the
selected memory component. Range: 0x00–0x0F
This field contains the data to be written or read from the memory test address for
the selected memory component. Range: 0x00–0xFF
Reserved. Set to 0
Reserved. Set to 0
This field contains the most significant bit of the SRAM write counter for the
diagnostic link (selected using the field below).
This field contains the PHY Cell Bus Address of the port for which a diagnostic
measurement is to be performed. Range: 0x00–0x1F
Description
Description
Description
™
Registers
7
-
71