cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 39

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
Table 2-3. CX2822x Pin Descriptions (6 of 12)
28229-DSH-001-D
phyURxData[0]
phyURxData[1]
phyURxData[2]
phyURxData[3]
phyURxData[4]
phyURxData[5]
phyURxData[6]
phyURxData[7]
phyURxSOC
phyUTxAddr[0]
phyUTxAddr[1]
phyUTxAddr[2]
phyUTxAddr[3]
phyUTxAddr[4]
phyUTxClAv[0]
phyUTxClAv[1]
phyUTxClk
phyUTxData[0]
phyUTxData[1]
phyUTxData[2]
phyUTxData[3]
phyUTxData[4]
phyUTxData[5]
phyUTxData[6]
phyUTxData[7]
phyUTxEnb[0]*
phyUTxEnb[1]*
phyUTxSOC
Pin Label
PHY UTOPIA Receive
Data
PHY UTOPIA Start of
Cell
PHY UTOPIA
Transmit Address
PHY UTOPIA
Transmit Cell
Available
PHY UTOPIA
Transmit Clock
PHY UTOPIA
Transmit Data
PHY UTOPIA
Transmit Enable
PHY UTOPIA
Transmit Start of Cell
Signal Name
Mindspeed Technologies
M13
M14
M15
No.
P10
T12
R12
P13
N13
N14
T14
T13
R13
L15
K13
R14
R15
T15
R16
P15
N15
P16
N16
L13
C14
E16
R9
P9
T9
I/PD
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Received 8 bit PHY Cell Data. All received cells are passed
to the internal IMA processor.
Start of Cell synchronization signal for Receive PHY cells
(active high). Indicates that the first byte of the cell is being
placed on the PhyURxData[7:0] bus.
Transmit PHY Cell Bus address. The following limitations
apply:
Cell Available signals for Transmit ATM cells. When
phyUTxClAv[n] is active high, the PHY has space available
for one or more complete cells. To support different PHY
devices, separate cell available signals are provided.
PhyUTxClAv[1] is a No Connect on the CX28224/5 devices.
IMA_SysClk divided by two.
8 bit PHY Cell Data to be sent out the PHY facility.
8 bit UTOPIA interface used to transmit data to the external
TC devices.
Data transfer enable for Transmit PHY cells (active low
signal). To support different PHY devices, separate enable
signals are provided.
Start of Cell synchronization signal for Transmit PHY cells
(active high). Indicates that the first byte of a cell is being
placed on the phyUTxData[7:0] bus.
CX28224
CX28225
CX28229
Device
™
Description
CX2822x Hardware Description
Addresses
0, 1, 31
0–3, 31
0–31
2
-
11