cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 38

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX2822x Hardware Description
Table 2-3. CX2822x Pin Descriptions (5 of 12)
2-10
TRST*
TCK
TMS
TDI
TDO
TestEnable
TestMode
PhyIntFcSel
phyURxClk
phyURxEnb[0]*
phyURxEnb[1]*
phyURxAddr[0]
phyURxAddr[1]
phyURxAddr[2]
phyURxAddr[3]
phyURxAddr[4]
phyURxClAv[0]
phyURxClAv[1]
Pin Label
Test Reset
Test Clock
Test Mode Select
Test Data Input
Test Data Output
PHY Interface Select
UTOPIA Receive
Clock
PHY UTOPIA Receive
Enable
PHY UTOPIA Receive
Address
PHY UTOPIA Receive
Cell Available
Signal Name
Mindspeed Technologies
No.
E14
P14
T16
E13
F13
F16
F15
R4
R7
N8
R8
N9
T3
T4
T6
T7
P8
T8
I/PU
I/PU
I/PU
I/PD
I/O
O
O
O
O
I
I
I
I
I
When asserted, the internal boundary-scan logic is reset.
This pin has a pull-up resistor.
Note: In accordance with the IEEE 1149.1 specification, it
is recommended that TRST* be held low until power is
stable in order to ensure deterministic operation. This can
be done by connecting the TRST* pin to the Reset* pin.
Note: When JTAG is not used, this pin should be tied either
directly to ground or though a 1K or less pull down
resistor.
Samples the value of TMS and TDI on its rising edge to
control the boundary scan operations.
Controls the boundary-scan Test Access Port (TAP)
controller operation. This pin has a pull-up resistor.
The serial test data input. This pin has a pull-up resistor.
The serial test data output.
Factory test use only, tie to VSS.
Factory test use only, tie to VSS.
If this pin is tied low, the PHY UTOPIA Interface mode is
selected. This table shows pin configurations with this pin
tied low.
If this pin is tied high, the PHY Serial mode is selected.
IMA_SysClk/2
Data transfer and output enable for Receive PHY cells
(active low). To support multiple PHY devices, separate
enable signals are provided. Depending on the software
configuration, some of the enable signals may not be
available and will be replaced by additional PHY cell bus
address bits. PhyURxEnb[1] is a No Connect on the
CX28224/5 devices.
Receive PHY Cell Bus address. The following limitations
apply:
Cell Available signals for Receive PHY interfaces.
phyURxClAv{n] is active when one or more complete cells
can be transferred. To support different PHY devices,
separate cell available signals are provided. This allows
expansion to 32 points. PhyURxClAv[1] is a No Connect on
the CX28224/5 devices.
CX28224
CX28225
CX28229
Device
™
Description
Addresses
0, 1, 31
0–3, 31
0–31
CX28224/5/9 Data Sheet
28229-DSH-001-D