cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 136

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

Registers
7-36
FOOTNOTE:
(1)
Bit
These bits should only be changed when the device or port logic reset is asserted.
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0x05—IOMODE (Input/Output Mode Control Register)
RxSyncPol
RxClkPol
TxSyncPol
TxClkPol
The IOMODE register controls the line interface signal polarities and status outputs.
Name
(1)
(1)
—
—
—
—
(1)
(1)
Mindspeed Technologies
Reserved, set to 0.
This bit determines the Receiver Synchronization input Polarity. When written to a
logical 1, the active level on the SPRxSync input is high. When written to a logical 0,
the active level is low.
This bit determines the Receiver Clock Input Polarity. When written to a logical 1,
the active edge on the SPRxClk input is the falling edge. When written to a logical 0,
the active edge is the rising edge.
This bit determines the Transmitter Synchronization input Polarity. When written to
a logical 1, the active level on the SPTxSync input is high. When written to a logical
0, the active level is low.
This bit determines the Transmitter Clock Input Polarity. When written to a logical 1,
the active edge on the SPTxClk input is the falling edge. When written to a logical 0,
the active edge is the rising edge.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Description
™
CX28224/5/9 Data Sheet
28229-DSH-001-D