cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 47

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
Figure 2-4. CX28229 Logic Diagram (UTOPIA-to-Serial)
28229-DSH-001-D
Address Strobe, Write Control
ATM Transmit Address Bus
ATM Receive Address Bus
Write/Read, Read Control
Sync/Async Mode Select
External Memory Select
Microprocessor Clock
Receive Data Marker
Receive Data Marker
IMA Reference Clock
ATM Transmit Enable
ATM Receive Enable
PHY Interface Select
ATM Transmit Clock
ATM Receive Clock
Memory Data Bus
IMA System Clock
Test Mode Select
Test Data Input
Receive Clock
Receive Clock
Receive Data
Receive Data
8kHzIn Clock
Address Bus
Chip Select
Test Enable
Test Reset
Test Clock
Test Mode
Reset
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ExtMemSel
atmURxEnb*
IMA_SysClk
atmURxClk
atmURxAddr[4:0]
IMA_RefClk
MemData[15:0]
MAS*, MWr*
TRST*
atmUTxClk
atmUTxEnb*
atmUTxAddr[4:0]
PhyIntFcSel
MSyncMode
MicroClk
MCS*
MicroAddr[10:0]
TCK
TMS
TDI
TestEnable
TestMode
Reset*
8kHzIn
SPRxClk[0]
SPRxData[0]
SPRxSync[0]
MW/R, MRd*
SPRxClk[7]
SPRxData[7]
SPRxSync[7]
Mindspeed Technologies
ATM UTOPIA Transmit
ATM UTOPIA Receive
(1)
External Memory
Microprocessor
JTAG Interface
Line Interface
Line Interface
One Second
IMA Clocks
Interface
Interface
Interface
Interface
Interface
Reset
Port 0
Port 7
. .
.
atmURxData[15:0]
atmUTxData[15:0]
MemCtrl_ADSC
MemAddr[19:0]
MicroData[7:0]
MemCtrl_WE*
MemCtrl_OE*
MemCtrl_CE*
SPTxSync[0]
SPTxSync[7]
atmURxSOC
MemCtrl_Clk
SPTxData[0]
SPTxData[7]
atmURxClAv
atmUTxSOC
atmUTxClAv
atmURxPrty
StatOut[1:0]
atmUTxPrty
SPTxClk[0]
SPTxClk[7]
TxTRL[1:0]
OneSecIO
MicroInt*
MRdy
TDO
™
I/O
I/O
I/O
I/O
O
O
O
O Write Enable
O
O
O Status Output
O Summary Interrupt
O
O
O
O
O
O
O ATM Receive Data Bus
O Transmit Reference Clock
O
O Address Enable
I
I
I
I
I
One Second Input/Output
Transmit Clock
Transmit Data
Transmit Data Marker
Transmit Clock
Transmit Data
Transmit Data Marker
Ready
Microprocessor Data Bus
Test Data Output
ATM Transmit Cell Available
ATM Transmit Start Of Cell
ATM Transmit Parity
ATM Transmit Data Bus
ATM Receive Cell Available
ATM Receive Start of Cell
ATM Receive Parity
Memory Address Bus
Chip Enable
Output Enable
SRAM Clock
CX2822x Hardware Description
(1) Pulled High
500027_003
2
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19