cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 67

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

28229-DSH-001-D
3
IMA Clocks
In order to maintain transmit frame synchronization the IMA engine must know the
exact cell rate of each group. This is provided by the Transmit IMA Data Cell Rate
clock (Tx IDCR). In addition, to operate the Receive Cell Smoothing buffer the
device must know the Receive IMA Data Cell Rate (Rx IDCR). There is a Tx IDCR
and Rx IDCR for each of the 16 groups that the CX29229 supports.
The CX29229 provides for tremendous flexibility with regard to these clocks. An
oveview of the clocking circuitry is shown in
overwhelming at first glance, most applications are actually quite straightforward.
The situation is also simplified by the software driver; it will calculate and program
most of the control registers automatically. The hardware designer only needs to
ensure that the proper clocks are available for the architecture desired.
In addition, two clock outputs are also provided: Tx_TRL[1] and Tx_TRL[0]. These
can be used to output one of the reference clock inputs or generate an 8 kHz reference
that is phase locked to IMA_SysClk or IMA_RefClk (whichever is used as a timing
reference).
The IDCR Clocks can be derived from one of four input sources:
1.
2.
3.
4.
IMA_SysClk: This is the primary IMA system clock and is used by most of the
internal IMA logic. It is also used to generate the PHY side UTOPIA Rx and Tx
clocks (phyURxClk and phyUTxClk).
IMA_RefClk: This is used with applications where multiple Transmit references
are available and/or when it is possible or necessary to run asynchronously
relative to IMA_SysClk. This signal is either a line or payload rate reference
clock or is a high speed (n
and Receive payload rates can be derived.
Receive bit clock: When operating in the UTOPIA-to-Serial mode the CX2822x
can select any of the Rx bit clocks to use as the reference clock. The receive
direction timing is used for recovering the IMA frame rate of the received IMA
group. Using this option for the Transmit IMA group frame rate results in a 'line
timed' configuration.
phyURxClAv: This is the PHY side UTOPIA Rx Cell Available signal, which
tracks the actual cell data rate being transferred from an individual port. Internal
synthesizers can use this signal in place of the serial Rx bit clocks to derive the
payload rate for each Receive port. The receive direction timing is used for
recovering the IMA frame rate of the received IMA group. Using this option for
the Transmit IMA group frame rate results in a 'line timed' configuration.
Mindspeed Technologies
x
8 kHz) reference clock from which nominal Transmit
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Figure
3-1. While this can appear to be
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