cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 155

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
28229-DSH-001-D
FOOTNOTE:
(1)
(2)
Bit
Dual event—Either a 0 to 1 or a 1 to 0 transition on the corresponding status bit causes this interrupt to occur, provided that
this interrupt has been enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt.
Single event—A 0 to 1 transition on the corresponding status bit causes this interrupt to occur, provided that this interrupt has
been enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt.
7
6
5
4
3
2
1
0
Default
—
—
—
—
—
—
—
—
0x2D—RXCELLINT (Receive Cell Interrupt Indication Status Register)
LOCDInt
HECDetInt
HECCorrInt
CellRcvdInt
IdleRcvdInt
NonMatchInt
NonZerGFCInt
The RXCELLINT register indicates that a change of status has occurred within the
receive status signals.
Name
(1)
—
(2)
(2)
(2)
(2)
(2)
(2)
Mindspeed Technologies
When a logical 1 is read, this bit indicates that a Loss of Cell Delineation has
occurred.
When a logical 1 is read, this bit indicates that a HEC Error was detected.
Reserved, write to a logical 0.
When a logical 1 is read, this bit indicates that a cell has been received.
When a logical 1 is read, this bit indicates that an Idle Cell has been received.
When a logical 1 is read, this bit indicates that a Non-matching Cell has been
received.
When a logic 1 is read, this bit indicates that a Non-zero GFC has been received.
When a logical 1 is read, this bit indicates that a HEC Error was corrected.
Description
™
Registers
7
-
55