cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 97

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
6.1.2.2
28229-DSH-001-D
Interrupts
The CX2822x’s interrupt indications can be classified as either single- or dual-event;
a single-event interrupt is triggered by a status assertion; a dual-event interrupt is
triggered by either a status assertion or deassertion. Both types of interrupts are
further described in the following examples.
Single-event interrupt: When a parity error occurs on the UTOPIA transmit data bus,
an interrupt is generated on ParErrInt, bit 7, in the TXCELLINT register (0x2C). This
bit is cleared when read.
Dual-event interrupt: When LOCD occurs, bit 7 of the corresponding RXCELLINT
register (0x0D) is set to 1. This bit is cleared when the register is read. Once cell
delineation is recovered, bit 7 is set to 1 again, generating another interrupt.
All interrupt bits have a corresponding enable bit. This allows software to disable or
mask interrupts as required.
The CX2822x uses three levels of interrupt indications. The first level consists of
receive or transmit interrupt indications, which correspond to specific events on a
specific port. The second level summarizes first level interrupts and indicates framer
and one-second interrupts for each port. The third level indicates which port generated
an interrupt.
The first level interrupt indications are located in registers TXCELLINT and
RXCELLINT for each port. Each interrupt bit in these registers can be disabled in the
corresponding ENCELLR or ENCELLT register, respectively. The result is then
ORed into the appropriate bit in the port’s SUMINT register.
The second level consists of summary interrupt indications, located in the SUMINT
register. It also includes the OneSecInt and the ExInt indications. Each interrupt bit in
these registers can be disabled in the corresponding ENSUMINT register. The result
is then ORed into the appropriate bit in the SUMPORT register.
The third level contains the overall interrupt indications for each port in the
SUMPORT register. These bits can be disabled in the ENSUMPORT register. The
result is ORed to the MicroInt* pin. The MicroInt* pin can be enabled or disabled by
setting the EnIntPin (bit 3) in the MODE register (0x202).
Figure 6-1
illustrates the registers involved in the interrupt generation process.
NOTE:
illustrates the flow chart of the interrupt generation process and
The IMA block does not generate interrupts.
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General Issues
Figure 6-2
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