cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 52

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX2822x Hardware Description
Table 2-5. CX28229 Pin Descriptions (3 of 12)
2-24
MRdy
MicroClk
ExtMemSel
MemData[0]
MemData[1]
MemData[2]
MemData[3]
MemData[4]
MemData[5]
MemData[6]
MemData[7]
MemData[8]
MemData[9]
MemData[10]
MemData[11]
MemData[12]
MemData[13]
MemData[14]
MemData[15]
Pin Label
Microprocessor
Ready
Microprocessor
Clock
External Memory
Enable
Differential Delay
Memory Data Bus
Signal Name
Mindspeed Technologies
N10
R10
N11
R11
N12
No.
C13
T10
P11
T11
P12
R3
R6
N7
T2
T5
P6
P7
A6
B6
I/O/PD
I/PD
I/O
O
I
When active high, the current read or write transaction has
been completed. For a read transaction, the data is ready to
be transferred to the microprocessor. For a write
transaction, the data provided by the microprocessor has
been written. This pin is an open drain output for an
external wired OR logic implementation. An external pull-
up resistor is required for this pin.
An 8–50 MHz clock signal input. The device samples the
microprocessor interface pins (MCS*, MW/R, MAS*,
MicroAddr[10:0], and Microdata[7:0]) on the rising edge
of this signal. The microprocessor interface output pins
(Microdata[7:0], MicroInt*) are clocked on the rising edge
of MicroClk. Note that this clock is required for both
synchronous and asynchronous operations. See note in
Section
When this pin is pulled high, it enables the external
differential delay SRAM bus.
Differential delay SRAM Data Bus. ATM cells extracted
from the Receive data stream are stored in the SRAM for
the purpose of differential delay compensation.
This bus is enabled by pulling the ExtMemSel pin high.
6.1.
™
Description
CX28224/5/9 Data Sheet
28229-DSH-001-D