cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 104

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

Registers
Table 7-3. Port Control and Status Registers (3 of 3)
Table 7-4. General Use Registers
7-4
FOOTNOTE:
(1)
(2)
0x200
0x04
0x05
0x203
Port Offset
Port Offset
Address
Address
One-second latching is enabled by setting EnStatLat (bit 5) in the MODE register (0x0202) to a logical 1.
One-second latching is enabled by setting EnCntrLat (bit 4) in the MODE register (0x0202) to a logical 1.
0x3A
0x3B
0x3C
0x3D
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3E
0x3F
IDLCNTM
IDLCNTH
LOCDCNT
TXCNTL
TXCNTM
TXCNTH
CORRCNT
RXCNTL
RXCNTM
RXCNTH
UNCCNT
NONCNTL
NONCNTH
MODE
PMODE
IOMODE
OUTSTAT
Name
Name
—
—
Table 7-4
device- and port-level operating modes.
Table 7-5
Device Mode Control Register
Port Mode Control Register
Input/Output Mode Control Register
Output Pin Control Register
Type
—
—
R
R
R
R
R
R
R
R
R
R
R
R
R
lists several registers used for CX2822x’s basic functions, including
lists the control registers used for transmission of traffic.
One-second
Mindspeed Technologies
Latching
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
—
—
Idle Cell Receive Counter (middle byte)
Idle Cell Receive Counter (high byte)
LOCD Event Counter
Transmitted Cell Counter (low byte)
Transmitted Cell Counter (mid byte)
Transmitted Cell Counter (high byte)
Corrected HEC Error Counter
Received Cell Counter (low byte)
Received Cell Counter (mid byte)
Received Cell Counter (high byte)
Uncorrected HEC Error Counter
Non-Matching Cell Counter (low byte)
Non-Matching Cell Counter (high byte)
Reserved, set to a logical 0
Reserved, set to a logical 0
Description
Description (Continued)
™
CX28224/5/9 Data Sheet
28229-DSH-001-D
page 7-64
page 7-35
page 7-36
page 7-65
page 7-57
page 7-58
page 7-58
page 7-59
page 7-59
page 7-60
page 7-60
page 7-61
page 7-61
page 7-62
page 7-62
page 7-63
page 7-63
Number
Number
Page
Page
—
—