cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 134

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

Registers
7-34
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0x01—ENSUMINT (Summary Interrupt Control Register)
EnOneSecInt
EnTxCellInt
EnRxCellInt
The ENSUMINT register controls which of the interrupts listed in the SUMINT
register (0x00) appear in the SUMPORT register and on the MicroInt* (pin T1),
provided the corresponding ENSUMPORT bit is enabled and EnIntPin (bit 3) in the
MODE register (0x0202) is enabled.
Name
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Mindspeed Technologies
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
When written to a logical 1, this bit enables the one-second interrupt generated by
the OneSecIO pin (pin R5) to appear on the MicroInt* output pin (pin T1).
Reserved, set to a logical 0.
When written to a logical 1, this bit enables the transmit cell interrupts located in the
TxCellInt register (0x2C). These interrupts appear can on the MicroInt* pin (pin T1),
provided that EnPortInt in the ENSUMPORT register (0x0201) is enabled for this
port and EnIntPin (bit 3) in the MODE register (0x0202) is enabled.
When written to a logical 1, this bit enables the receive cell interrupts located in the
RxCellInt register (0x2D). These interrupts can appear on the MicroInt* pin (pin T1),
provided that EnPortInt in the ENSUMPORT register (0x0201) is enabled for this
port and EnIntPin (bit 3) in the MODE register (0x0202) is enabled.
Description
™
CX28224/5/9 Data Sheet
28229-DSH-001-D