cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 68

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

IMA Clocks
Table 3-1. IMA Block Clock Sections
3-2
Serial Port Synchronizer This block contains a transition detector and a synchronizer. It synchronizes the clocks from the TC
IMA_SysClk Dividers
IMA_RefClk
Synchronizer
IDCR Source Mux
Rx IDCR Clock
Tx IDCR Clock
Bit Rate Clock Generator This block generates a clock that represents the link data rate. It can generate 16 independent Tx and 16
Digital Phase Locked
Loop
Clock Section
block Serial ports to the IMA_SysClk divided by 16. It handles all 8 internal serial ports independently.
This block contains two dividers: a divide by 16 and a divide by 24. The divide_16 is used to synchronize
external clocks to internal logic. The divide_24 allows the IMA_SysClk to be used to generate both the
Rx IDCR and the Tx IDCR clocks (provided that IMA_SysClk is 24 times the bit rate).
This block contains a transition detector and a synchronizer. It synchronizes the IMA_RefClk to the
IMA_SysClk divided by 16.
This software controlled mux selects which clock sources are feed to the appropriate IDCR clock
dividers.
length (M), number of links in the group (N), frame payload (P) and frame bit (F). (The 2048/2049 factor
results from the IMA standards requirement of inserting a stuff event every 2048 cells.) This block can
generate 16 independent Rx IDCR clock outputs (one per group).
This block divides the bit rate clock down to a Link cell data rate clock based on the values of frame
length (M), number of links in the group (N), frame payload (P) and frame bit (F). (The 2048/2049 factor
results from the IMA standards requirement of inserting a stuff event every 2048 cells.) This block can
generate 16 independent Rx IDCR clock outputs (one per group).
independent Rx clocks. In normal operation, all parameters are configured automatically by the software
driver. It contains the following blocks:
This block generates a bit rate clock that is phase locked to the PHY side RxClAv signal. It can monitor
all 32 ports on the bus. Any port can be selected as the group timing reference.
This block divides the bit rate clock down to a link cell data rate clock based on the values of frame
Figure 3-1
block is responsible for generating all clocks required by the IMA engine. It can be
further divided into 8 sections, as shown in
Pre-scaler—This block divides the selected input (either IMA_RefClk or IMA_SysClk) by the factor
Synchronizer—Synchronizes the Pre-Scaler output to the internal logic using the IMA_SysClk
Numerically Controlled Oscillator—This clock circuit generates the link bit rate.
of Pnum divided by Pden.
divided by 16.
shows the details of the CX28229's IMA clock block from
Mindspeed Technologies
Description
Table
™
3-1:
CX28224/5/9 Data Sheet
Figure
28229-DSH-001-D
1-1. This