cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 190

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

Registers
7-90
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0x61F—IMA_GRP_9TO12_SEM (Group Table Control III (CX28229 Only))
Update Enable for Receive group 12
Update Enable for Receive group 11
Update Enable for Receive group 10
Update Enable for Receive group 9
Update Enable for Transmit group 12
Update Enable for Transmit group 11
Update Enable for Transmit group 10
Update Enable for Transmit group 9
For the following bits, 1 = the group table is being updated, 0 = the group table is not
being updated. The update enable must be set to 1 prior to writing the group table. All
elements of the group table must be re-written. After writing to all 8 elements, the
update enable is reset to 0. The group tables are described below.
NOTE:
Name
This register cannot be read back.
Mindspeed Technologies
addresses 0x6DC–0x6DF (Not defined for CX28224 and CX28225)
addresses 0x6D8–0x6DB (Not defined for CX28224 and CX28225)
addresses 0x6D4–0x6D7 (Not defined for CX28224 and CX28225)
addresses 0x6D0–0x6D3 (Not defined for CX28224 and CX28225)
addresses 0x638–0x63F (Not defined for CX28224 and CX28225)
addresses 0x630–0x637 (Not defined for CX28224 and CX28225)
addresses 0x628–0x62F (Not defined for CX28224 and CX28225)
addresses 0x620–0x627 (Not defined for CX28224 and CX28225)
™
Description
CX28224/5/9 Data Sheet
28229-DSH-001-D