cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 157

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cx28224

Manufacturer Part Number
cx28224
Description
Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
Manufacturer
Mindspeed Technologies
Datasheet
CX28224/5/9 Data Sheet
28229-DSH-001-D
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0x30—IDLCNTL (Idle Cell Receive Counter [Low Byte])
0x31—IDLCNTM (Idle Cell Receive Counter [Mid Byte])
IdleCnt[7]
IdleCnt[6]
IdleCnt[5]
IdleCnt[4]
IdleCnt[3]
IdleCnt[2]
IdleCnt[1]
IdleCnt[0]
IdleCnt[15]
IdleCnt[14]
IdleCnt[13]
IdleCnt[12]
IdleCnt[11]
IdleCnt[10]
IdleCnt[9]
IdleCnt[8]
The IDLCNTL counter tracks the number of received idle cells. This byte of the
counter should be read first. The counter is cleared on read.
The IDLCNTM counter tracks the number of received cells. The counter is cleared on
read.
Name
Name
Mindspeed Technologies
Received cell counter bit 7.
Received cell counter bit 6.
Received cell counter bit 5.
Received cell counter bit 4.
Received cell counter bit 3.
Received cell counter bit 2.
Received cell counter bit 1.
Received cell counter bit 0 (LSB).
Received cell counter bit 15.
Received cell counter bit 14.
Received cell counter bit 13.
Received cell counter bit 12.
Received cell counter bit 11.
Received cell counter bit 10.
Received cell counter bit 9.
Received cell counter bit 8.
Description
Description
Registers
7
-
57

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