cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 87

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
Table 5-1. Control Bit Functions
28229-DSH-001-D
GENERAL NOTE:
1. The HEC Error Correction circuit is independent of the DisHECChk control bit. The CX28229 will correct single bit errors even
DisLOCD
when the DisHECChk is enabled (assuming that the EnHECCor bit is set to 1).
0
0
1
1
DisHECChk
0
1
0
1
Normal operation; used for standard ATM traffic.
Cells are output to the UTOPIA FIFO only after cell delineation is found. Only cells with valid HECs
are passed (this includes cells with single bit errors that have been corrected).
Ignore HEC Errors Mode; used for IMA applications.
The Cell Delineator state machine is active and looking for valid ATM cells. It will follow the ATM
Forum’s Cell Delineation process. However, since the Cell Valid State machine is turned off, the
CX28229 will pass all cells, including those with HEC errors, to the UTOPIA FIFOs.
The CX28229 will not transfer cells during LOCD.
The cell delineation function is disabled and every 53 bytes of incoming data is treated as a ‘cell’.
However, since the CV machine is still active, only cells with valid HECs will be output. As a result,
almost all data will be dropped. Occasionally, random data will have what appears to be a valid
HEC and will be output. Mindspeed is not aware of any use for this mode.
Raw Data mode; allows the CX28229 to be used as a generic ‘serial to parallel’ convertor.
All data received will be passed across the UTOPIA bus in blocks of 53 bytes. No attempt is made
to find ATM cells.
Mindspeed Technologies
Description
™
Transmission Convergence Block
5
-
5