cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 74

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

IMA Clocks
3.1.2
3-8
DSL/T1/E1 Using UTOPIA-to-UTOPIA Interfaces
Figure 3-4
require more than 8 ports. Up to 32 links and 16 groups can be supported using
external Cell Delineators such as the RS8228.
The device is configured using a software driver. The following code is an example of
calls to the driver:
The Rx IDCR clock is synthesized using the RxClAv input from the PHY side
UTPOIA bus. This is performed on a per group basis; that is, one link in each
group is selected (via software) to provide the Rx IDCR for that group.
IMA_SysClk must be greater than or equal to 40.96 MHz (less than 24 ports) and
be greater than or equal to 49.152 MHz if there are more than 24 ports.
Either IMA_SysClk or IMA_RefClk can be used as the Tx IDCR clock:
IMA_LINK_TYPE = IMA_VAR_RATE
IMA_DSL_REF_CLK_FREQUENCY = 40960000
IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE
IMA_DSL_REF_GENERATOR = IMA_ACTIVE
IMA_ALT_RX_TRL = IMA_ACTIVE
IMA_GRP_LINK_BANDWIDTH = 2304 (grp#)
IMA_GRP_CLK_REF_FACTOR = IMA_NO_DIV (grp#)
IMA_GRP_TX_TRL_SRC = IMA_REF_XCLK (grp#)
IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#)
IMA_SysClk may be used if it is an 8 kHz multiple of the bit rate.
IMA_RefClk may be used if it is an 8 kHz multiple of the bit rate and greater
than or equal to 4.64 MHz.
illustrates the configuration most commonly used with applications that
Mindspeed Technologies
™
CX28224/5/9 Data Sheet
28229-DSH-001-D