cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 85

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
5.2.1
Figure 5-2. Cell Delineation Process
28229-DSH-001-D
Cell Delineation
The ATM block receives octets from the framers and recovers ATM cells by means of
cell delineation. Cell delineation is achieved by aligning ATM cell boundaries using
the HEC algorithm. Four consecutive bytes are chosen and the HEC value is
calculated. The result is compared with the value of the following byte. This “hunt” is
continued by shifting this four-byte window, one byte at a time, until the calculated
HEC value equals the received HEC value. When this occurs, a pre-sync state is
declared and the next 48 bytes are assumed to be payload. The ATM block calculates
HEC on the four bytes following this payload, assuming that a new cell has begun. If
seven consecutive header blocks are found, synchronization is declared. If any HEC
calculation fails in the pre-sync state, the process begins again (see
Synchronization will be held until seven consecutive incorrect HECs are received. At
this time, the “hunt” state is reinitiated.
During the sync state of cell delineation, cells are passed to the UTOPIA interface if
the HEC is valid. If a single-bit error in the header is detected, the error is corrected
(optionally), and the cell is passed to the UTOPIA interface. If HEC checking is
enabled and HEC correcting is disabled (bit 3 in the CVAL register [0x0C]), cells
with single-bit HEC errors are discarded. If a multi-bit error is detected, the cell is
dropped. Once either type of error is noted, all subsequent errored cells are dropped
until a valid cell is received. This rule applies even for single-bit errors that could be
corrected. Once a valid cell is detected, the process begins again. (See
When loss-of-cell delineation (LOCD) occurs, an interrupt is generated and the
CX2822x automatically enters the “hunt” mode. However, the cell is still being
scrambled by the far-end transmitter, leaving only the headers (or just the HEC byte in
Distributed Sample Scrambler [DSS]) unscrambled. This means that the only
repetitive byte patterns in the data stream that meet the cell delineation criteria are
valid headers (or just the HEC bytes in DSS).
Hunt
1 Correct HEC
Mindspeed Technologies
7 Errored HECs
1 Errored HEC
Pre-Sync
™
Sync
6 Correct HECs
Transmission Convergence Block
Figure
Figure
5-2).
5-3.)
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