cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 137

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
28229-DSH-001-D
Bit
7
6
5
4
3
2
1
0
Default
0
1
1
0
0
0
0
0
0x08—CGEN (Cell Generation Control Register)
DisHEC
EnTxCos
EnTxCellScr
ErrHEC
DSLSyncPol
EnTxDSSScr
EnRxDSSScr
The CGEN register controls the device’s cell generation functions.
Name
—
Mindspeed Technologies
When written to a logical 1, this bit disables internal generation of the HEC field.
When disabled, the HEC field from the UTOPIA interface remains unchanged in the
transmitted cell. When written to a logical 0, HEC is internally calculated and
inserted in the transmitted cell.
When written to a logical 1, this bit enables the Transmit HEC Coset. When written to
a logical 0, the HEC Coset is disabled.
When written to a logical 1, this bit enables the Transmit Cell Scrambler. When
written to a logical 0, the Transmit Cell Scrambler is disabled.
When written to a logical 1, this bit causes the ERRPAT register to be XORed with
the calculated HEC byte for one transmit cell. These bits are cleared automatically by
internal circuitry after the indicated error insertion has taken place. Clearing takes
precedence over a simultaneous write operation to this register.
This bit controls the polarity of the sync pulse in DSL mode. Set to 1 for active high
and to 0 for active low.
Reserved, write to a logical 0.
When written to a logical 1, this bit enables the Transmit DSS Scrambler. When
written to a logical 0, the Transmit DSS Scrambler is disabled.
When written to a logical 1, this bit enables the Receive DSS Scrambler. When
written to a logical 0, the Receive DSS Scrambler is disabled.
Description
™
Registers
7
-
37