cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 70

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

IMA Clocks
3.1
3.1.1
3.1.1.1
3-4
Common Applications
T1/E1 Using Internal Serial Ports
The solution for high port count and variable rate DSL applications is to use internal
counters and frequency synthesizers referenced from a common (n
input with feedback from the cell available signal from the PHY side UTOPIA bus.
For low port count, single rate applications that take advantage of the embedded ATM
Cell Processor, the use of receive bit clock inputs is the most straight-forward
solution.
Several of the most common applications follow.
Using IMA_SysClk as the Transmit Clock
Figure 3-2
24 times the line rate. This is one of the simplest implementation of IMA when a
clock equal to 24 times the line rate is available. Several issues are worth noting:
The device is configured using a software driver. The following code is an example of
calls to the driver:
The IMA_RefClk input is unused and should be tied to ground. The CX28229 is
deriving all required clocks from the Serial port clocks and the IMA_SysClk.
The IMA_SysClk is used to synchronize the SPRxClk inputs to internal logic (via
the divide by 16 block).
The SPRxClk is being used to generate the Rx IDCR clock. Also note that the
receive clock from any link within a group could be used to generate the Rx IDCR
for that group.
The IMA_SysClk is being used to derive the TX IDCR clock.
IMA_LINK_TYPE = IMA_DS1
IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE
IMA_DSL_REF_GENERATOR = IMA_INACTIVE
IMA_ALT_RX_TRL = IMA_INACTIVE
IMA_GRP_TX_TRL_SRC = IMA_REF_XCLK (grp#)
IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#)
illustrates T1/E1 with internal serial ports, using IMA_SysClk equal to
Mindspeed Technologies
™
CX28224/5/9 Data Sheet
x
8 kHz) clock
28229-DSH-001-D