cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 154

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

Registers
7-54
FOOTNOTE:
(1)
Bit
Bit
Single event—A 0 to 1 transition on the corresponding status bit causes this interrupt to occur, provided that this interrupt has
been enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
—
—
—
—
—
—
1
1
1
0
1
1
1
1
0
0
0x29—ENCELLR (Receive Cell Interrupt Control Register)
0x2C—TXCELLINT (Transmit Cell Interrupt Indication Status Register)
EnLOCDInt
EnHECDetInt
EnHECCorrInt
EnCellRcvdInt
EnIdleRcvdInt
EnNonMatchInt
EnNonZerGFCInt
ParErrInt
SOCErrInt
TxOvflInt
RxOvflInt
CellSentInt
The ENCELLR register controls which of the interrupts listed in the RxCellInt
register (0x2D) appear on the MicroInt* pin (pin T1), provided that both EnRxCellInt
(bit 0) in the ENSUMINT register (0x01) and EnPortInt in the ENSUMPORT register
(0x0201) for this port are enabled, and EnIntPin (bit 3) in the MODE register
(0x0202) is enabled.
The TXCELLINT register indicates that a change of status has occurred within the
transmit status signals.
Name
Name
(1)
(1)
(1)
—
—
—
—
(1)
(1)
Mindspeed Technologies
When written to a logical 1, this bit enables a Loss of Cell Delineation Interrupt.
When written to a logical 1, this bit enables a HEC Error Detected Interrupt.
When written to a logical 1, this bit enables a HEC Error Corrected Interrupt.
Reserved, write to a logical 0.
When written to a logical 1, this bit enables a Cell Received Interrupt.
When written to a logical 1, this bit enables an Idle Cell Received Interrupt.
When written to a logical 1, this bit enables a Non-matching Cell Received Interrupt.
When written to a logical 1, this bit enables a Non-zero GFC Received Interrupt.
When a logical 1 is read, this bit indicates that a Parity Error occurred.
When a logical 1 is read, this bit indicates that a Start of Cell Error occurred.
When a logical 1 is read, this bit indicates that a Transmit FIFO Overflow occurred.
When a logical 1 is read, this bit indicates that a Receive FIFO Overflow occurred.
When a logical 1 is read, this bit indicates that a cell has been sent.
Reserved for factory test, ignore.
Reserved, set to a logical 0.
Reserved, write to a logical 0.
Description
Description
™
CX28224/5/9 Data Sheet
28229-DSH-001-D