cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 181

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
28229-DSH-001-D
3–0
7–0
7–0
7–0
7–0
7–1
7–0
Bit
7
6
5
4
0
Default
0x00
0x00
0x00
0x00
0x00
—
—
—
0
0
0
0
0x417—IMA_DSL_CLOCK_GEN_DATA (IMA_DSL Clock Generator Data)
EnRxSyn
DSLClkGen
IMA_ClkSel
Pre-scaler Terminal
Count
Pre-scaler Numerator This field contains the numerator for the pre-scaler.
Reference Clock
Divisor
Group Clock
Multiplier Factor
(lsbs)
Group Clock
Multiplier Factor
(msb)
Port Clock Multiplier
Factor (lsbs)
This register is used in conjunction with 0x416 to configure the operation of the DSL
Clock Generator in the IMA core. Register 0x416 and 0x417 are an indirect register
pair in that a particular clock generator element is selected using register 0x416 and
the configuration for that element is programmed using register 0x417.
Name
—
—
—
Mindspeed Technologies
Reserved. Set to 0.
Enable Rx Timing Synthesizers
Substitute DSL clock generator
register 0x411.
0 = Use IMA_SysClk as input to DSL Clock Generators
1 = Use IMA_RefClk as input to DSL Clock Generators
Reserved. Set to 0.
This field contains the terminal count of the pre-scaler clock divider. The pre-scaler
denominator is the value of this field plus 1.
This field contains 8 of the 9 bits of the terminal count for the reference clock
divisor. The reference clock divisor counts from 0 to the terminal count which is
given by the value of this field plus 257. As an example if the value of this register is
63 decimal, then the reference clock divisor will be 320.
This register contains the 8 lsbs of the payload bandwidth for the ports used in the
IMA group. The contents of this register are multiplied by 8kbps in order to obtain
the bandwidth.
Reserved. Set to 0.
This register contains the msb of the payload bandwidth for the ports used in the
IMA group. The contents of this register are multiplied by 2048kbps in order to
obtain the bandwidth.
This register contains the 8 lsbs of the payload bandwidth for the specific port of the
Rx Timing clock synthesizer. The contents of this register are multiplied by 8kbps in
order to obtain the bandwidth.
0 = Use SPRxClk inputs
1 = Use synthesizers instead of SPRxClk inputs
0 = Use IMA_SysClk/24 in IMA group clock and Tx_TRL selectors
1 = Use DSL Clock generator outputs when Timing Source is set to 0x20 in
For Control Type = 0
For Control Type = 1
For Control Type = 2
For Control Type = 3
For Control Type = 4
For Control Type = 5
For Control Type = 6
Description
™
Registers
7
-
81