cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 209

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

CX28224/5/9 Data Sheet
7.3 IMA Link Registers
28229-DSH-001-D
Bit
NOTE:This register cannot be read back.
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0x41E—IMA_LNK_SEM (Link Table Control Register)
Update Enable for Receive
facilities 24–31
Update Enable for Receive
facilities 16–23
Update Enable for Receive
facilities 8–15
Update Enable for Receive
facilities 0–7
Update Enable for
Transmit facilities 24–31
Update Enable for
Transmit facilities 16–23
Update Enable for
Transmit facilities 8–15
Update Enable for
Transmit facilities 0–7
The IMA Link layer contains configuration and status information that is associated
with IMA groups or pass-through facilities.
For the following bits, 1 = the link table is being updated, 0 = the link table is not
being updated. The update enable must be set to 1 prior to writing the link table. All
elements of the link table must be re-written. After writing to all 8 elements, the
update enable is reset to 0. The link tables are described below.
Name
Mindspeed Technologies
addresses 0x780–0x787, 0x7A8–0x7AF
addresses 0x680–0x687, 0x6A8–0x6AF
addresses 0x580–0x587, 0x5A8–0x5AF
addresses 0x480–0x487, 0x4A8–0x4AF
addresses 0x760–0x767, 0x770–0x777
addresses 0x660–0x667, 0x670–0x677
addresses 0x560–0x567, 0x570–0x577
addresses 0x460–0x467, 0x470–0x477
(Not defined for CX28224 and CX28225)
(Not defined for CX28224 and CX28225)
(Not defined for CX28224 and CX28225)
(Not defined for CX28224 and CX28225)
(Not defined for CX28224 and CX28225)
(Not defined for CX28224 and CX28225)
™
Description
Registers
7
-
109