cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 84

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

Transmission Convergence Block
5.1.1
5.2
Figure 5-1. Details of the TC Block (Bits 7 and 6 in ATMINTFC, address 0x202)
5-2
SPRxSync
SPTxSync
SPRxData
SPTxData
StatOut[0:1]
SPRxClkI
SPTxClk
Interface
Framer
(Line)
This segment is replicated for Ports 0 - 7
Loopback
Control
HEC Generation
ATM Cell Receiver
Interrupt Control
In normal operation, the CX2822x calculates the HEC for the four header bytes of
each cell coming from the ATM layer. It then adds the HEC coset (55 hex, by ATM
standards) and inserts the result in octet 5 of the outgoing cell. HEC calculation can be
disabled by setting bit 7 of CGEN (0x08) to a 1. When HEC is disabled, the CX2822x
leaves the contents of the HEC field unchanged and transmits whatever data is placed
in that field by the ATM layer.
The HEC coset is used to maintain a value other than zero in the HEC field. If the first
four bytes in the header are zero, the HEC derived from these bytes is also zero. When
this occurs and there are strings of zeros in the data, the receiver cannot determine cell
boundaries. Therefore, it is recommended that the value 55 hex be added to the HEC
before transmission. To enable the HEC coset on the transmit side, set bit 6 in register
CGEN (0x08) to one. To enable the receive HEC coset, set bit 5 in register CVAL
(0x0C) to one.
The ATM cell receiver performs cell delineation on incoming data cells by searching
for the position of a valid HEC field within the cell. The HEC coset can be either
active or inactive; this is determined in bit 5 in the CVAL (0x0C) register.
TCK
TC Transmit Port
TC Receive Port
TRST*
JTAG Controller
MicroInt*
TMS
TDI
Mindspeed Technologies
TDO
Alignment
Status and Control
Cell
ATM Cell Transmitter
ATM Cell Receiver
VPI/VCI Screening
Cell Validation
MicroAddr[10:0]
8kHzIn
One Second Interface
Microprocessor
MicroData[7:0]
™
Interface
4-cell
FIFO
4-cell
FIFO
OneSecIO
Control Lines
Transmit
UTOPIA
Receive
UTOPIA
Level 2
Level 2
IMA
IMA
CX28224/5/9 Data Sheet
UTOPIA
Level 2
Interface
atmUTxClk
atmUTxClAv
atmUTxEnb*
atmUTxSOC
atmUTxData[15:0]
atmUTxPrty
atmUTxAddr[4:0]
atmURxClk
atmURxClAv
atmURxEnb*
atmURxSOC
atmURxData[15:0]
atmURxPrty
atmURxAddr[4:0]
28229-DSH-001-D
500027_063