cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 138

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

Registers
7-38
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0x09—HDRFIELD (Header Field Control Register)
0x0A—IDLPAY (Transmit Idle Cell Payload Control Register)
InsGFC
InsVPI
InsVCI
InsPT
InsCLP
IdlPay[7]
IdlPay[6]
IdlPay[5]
IdlPay[4]
IdlPay[3]
IdlPay[2]
IdlPay[1]
IdlPay[0]
The HDRFIELD register controls the header insertion elements.
The IDLPAY register contains the transmit idle cell payload.
Name
Name
—
—
—
Mindspeed Technologies
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
When written to a logical 1, this bit inserts a Generic Flow Control (GFC) field in the
outgoing header from the TXHDR registers. When written to a logical 0, the GFC
field is not changed prior to transmission.
When written to a logical 1, this bit inserts a Virtual Path Identifier (VPI) field in the
outgoing header from the TXHDR registers. When written to a logical 0, the VPI field
is not changed prior to transmission.
When written to a logical 1, this bit inserts a Virtual Channel Identifier (VCI) field in
the outgoing header from the TXHDR registers. When written to a logical 0, the VCI
field is not changed prior to transmission.
When written to a logical 1, this bit inserts a Payload Type (PT) field in the outgoing
header from the TXHDR registers. When written to a logical 0, the PT field is not
changed prior to transmission.
When written to a logical 1, this bit inserts a Cell Loss Priority (CLP) bit in the
outgoing header from the TXHDR registers. When written to a logical 0, the CLP
field is not changed prior to transmission.
These bits hold the Transmit Idle Cell Payload values for outgoing idle cells.
Description
Description
™
CX28224/5/9 Data Sheet
28229-DSH-001-D