cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 164

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

Registers
7-64
2–1
Bit
7
6
5
4
3
0
Default
00
0
0
0
0
0
0
0x200—MODE (Device Mode Control Register)
DevMstRst
OneSecOut
DevLgcRst
EnStatLat
EnCntrLat
EnIntPin
Name
—
Mindspeed Technologies
Device master reset. When set high, all internal state machines in the TC block are
held in reset and all registers (except this bit) assume their default values.
Device logic reset. When set high, all internal state machines in the TC block are
held in reset but register values are unaffected.
When set to 1, the one-second status latching is enabled. The value of the status
bits are the events which occurred between the last two one-second events. Any
events occurring after the last one-second event is not reflected when the status
register is read. Those events are reflected in the status register upon the next one-
second event. When a status register is read, the status is cleared and is not
updated until the next one-second event.
When set to 0, the one-second status latching is disabled. The value of a status
register is the events occurred since the last read of the status register.
When set to 1, the one-second counter latching is enabled. The value of the
counter is the number of events counted between the last two one-second events.
Any events occurring after the last one-second event is not reflected when the
counter is read. Those events are reflected in the counter upon the next one-
second event. When a counter is read, the count is cleared and is not updated until
the next one-second event.
When set to 0, the one-second counter latching is disabled. The value of a counter
is the number of events counted since the last read of the counter.
Enables the MicroInt* output pin.
Reserved, set to zero.
When set to 1, the OneSecIO pin is configured as an output. The pin provides a
one-second event pulse. The one-second event is generated internally of the
device. The event occurs after the device has counted 8000 periods of a 8 KHz
clock.
When set to 0, the OneSecIO pin is configured as an input. The one-second event
must be genetared externally, by pulsing the OneSecIO pin for low-high-low.
™
Description
CX28224/5/9 Data Sheet
28229-DSH-001-D