SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 101

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
SuperI/O Module
4.3
This section describes the structure of the configuration
register file, and the method of accessing the configuration
registers.
4.3.1
The SIO configuration access is performed via an Index-
Data register pair, using only two system I/O byte locations.
The base address of this register pair is determined
according to the state of the IO_SIOCFG_IN bit field of the
Core Logic module (F5BAR0+I/O Offset 00h[26:25]). Table
4-1 shows the selected base addresses as a function of the
IO_SIOCFG_IN bit field.
The Index Register is an 8-bit R/W register located at the
selected base address (Base+0). It is used as a pointer to
the configuration register file, and holds the index of the
configuration register that is currently accessible via the
Data Register. Reading the Index Register returns the last
value written to it (or the default of 00h after reset).
The Data Register is an 8-bit virtual register, used as a
data path to any configuration register. Accessing the data
register results with physically accessing the configuration
register that is currently pointed by the Index Register.
4.3.2
Each functional block is associated with a Logical Device
Number (LDN). The configuration registers are grouped
into banks, where each bank holds the standard configura-
tion registers of the corresponding logical device. Table 4-2
shows the LDNs of the device functional blocks.
IO_SIOCFG_IN
Settings
CONFIGURATION STRUCTURE / ACCESS
Table 4-1. SIO Configuration Options
00
01
10
11
Index-Data Register Pair
Banked Logical Device Registers
Register
002Eh
015Ch
Index
I/O Address
-
-
(Continued)
Register
015Dh
002Fh
Data
-
-
SIO disabled
Configuration
access disabled
Base address 1
selected
Base address 2
selected
Description
101
Figure 4-3 shows the structure of the standard PnP config-
uration register file. The SIO Control And Configuration
registers are not banked and are accessed by the Index-
Data register pair only (as described above). However, the
Logical Device Control and Configuration registers are
duplicated over eight banks for eight logical devices. There-
fore, accessing a specific register in a specific bank is per-
formed by two-dimensional indexing, where the LDN
register selects the bank (or logical device), and the Index
register selects the register within the bank. Accessing the
Data register while the Index register holds a value of 30h
or higher results in a physical access to the Logical Device
Configuration registers currently pointed to by the Index
register, within the logical device bank currently selected by
the LDN register.
Banks
(One per Logical Device)
LDN
00h
01h
02h
03h
05h
06h
07h
08h
2Fh
07h
20h
30h
60h
74h
75h
FEh
63h
70h
71h
F0h
Figure 4-3. Structure of the Standard
Functional Block
Real-Time Clock (RTC)
System Wakeup Control (SWC)
Infrared Communication Port
(IRCP) or Serial Port 3 (SP3)
Serial Port 1 (SP1)
ACCESS.bus 1 (ACB1)
ACCESS.bus 2 (ACB2)
Parallel Port (PP)
Serial Port 2 (SP2)
Table 4-2. LDN Assignments
Configuration Register File
Logical Device Number Register
Logical Device Control Register
SIO Configuration Registers
Standard Logical Device
Special (Vendor-defined)
Configuration Registers
Standard Registers
Logical Device
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