SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 99
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SC2200
Manufacturer Part Number
SC2200
Description
Thin Client On a Chip
Manufacturer
NSC [National Semiconductor]
Datasheet
1.SC2200.pdf
(433 pages)
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Revision 3.0
SuperI/O Module
4.1
PC98 and ACPI Compliant
• PnP Configuration Register structure
• Flexible resource allocation for all logical devices:
Parallel Port
• Software or hardware control
• Enhanced Parallel Port (EPP) compatible with version
• EPP support for version EPP 1.7 of the Xircom specifi-
• EPP support as mode 4 of the Extended Capabilities
• IEEE 1284 compliant ECP, including level 2
• Selection of internal pull-up or pull-down resistor for
• PCI bus utilization reduction by supporting a demand
• Protection circuit that prevents damage to the parallel
• Output buffers that can sink and source 14 mA
Serial Port 1
• 16550A compatible (SIN1, SOUT1, DTR1#/BOUT1
Serial Port 2
• 16550A compatible
Serial Port 3 / Infrared (IR) Communication Port
• Serial Port 3
• IR Communication Port
— Relocatable base address
— 9 Parallel IRQ routing options
— 3 optional 8-bit DMA channels (where applicable)
EPP 1.9 and IEEE 1284 compliant
cation
Port (ECP)
Paper End (PE) pin
DMA mode mechanism and a DMA fairness mechanism
port when a printer connected to it powers up or is oper-
ated at high voltages, even if the device is in power-
down
signals only)
— SIN and SOUT signals only
— Data rate of up to 1.5 Mbps
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— DMA support
— IrDA 1.1 and 1.0 compatible
— Data rate of up to 115.2 Kbps (HP-SIR)
— Data rate of 1.152 Mbps (MIR)
— Data rate of 4.0 Mbps (FIR)
— Selectable internal or external modulation/demodula-
— Consumer-IR (TV-Remote) mode
— Consumer Remote Control supports RC-5, RC-6,
— DMA support
tion (ASK-IR and DASK-IR options of SHARP-IR)
NEC, RCA and RECS 80
FEATURES
(Continued)
99
System Wakeup Control (SWC)
• Power-up request upon detection of RI2#, CEIR, or
• Pre-programmed CEIR address in a pre-selected
• Powered by V
• Battery-backed wakeup setup
• Power-fail recovery support
Real-Time Clock
• A modifiable address that is referenced by a 16-bit
• DS1287, MC146818 and PC87911 compatibility
• 242 bytes of battery backed up CMOS RAM in two
• Selective lock mechanisms for the CMOS RAM
• Battery backed up century calendar in days, day of the
• Battery backed-up time of day in seconds, minutes and
• BCD or binary format for time keeping
• Three different maskable interrupt flags:
• Separate battery pin, 3.0V operation that includes an
• 7 µA typical power consumption during power down
• Double-buffer time registers
• Y2K Compliant
Clock Sources
• 48 MHz clock input
• On-chip low frequency clock generator for wakeup
• 32.768 KHz crystal with an internal frequency multiplier
SDATA_IN2 activity:
— Optional routing of power-up request on IRQ line
standard (any NEC, RCA or RC-5)
programmable register
banks
week, date of month, months, years and century, with
automatic leap-year adjustment
hours that allows a 12 or 24 hour format and adjust-
ments for daylight savings time
— Periodic interrupts - At intervals from 122 msec to
— Time-of-Month alarm - At intervals from once per
— Update Ended Interrupt - Once per second upon
internal UL protection resistor
to generate all required internal frequencies
500 msec
second to once per month
completion of update
SB
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