SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 160

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
5.2.5.6
The Core Logic module positively decodes memory
addresses
FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory
cycles cause the Core Logic module to claim the cycle, and
generate an ISA bus memory cycle with ROMCS#
asserted. The Core Logic module can also be configured to
respond to memory addresses FF000000h-FFFFFFFFh
(16 MB) and 000E0000h-000FFFFFh (128 KB).
8- or 16-bit wide ROM is supported. BOOT16 strap deter-
mines the width after reset. MCR[14,3] (Offset 34h) in the
General Configuration Block (see Table 3-2 on page 81 for
bit details) allows program control of the width.
Flash ROM is supported in the Core Logic module by
enabling the ROMCS# signal on write accesses to the
ROM region. Normally only read cycles are passed to the
ISA bus, and the ROMCS# signal is suppressed for write
cycles. When the ROM Write Enable bit (F0 Index 52h[1])
is set, a write access to the ROM address region causes a
write cycle to occur with MEMW#, WR# and ROMCS#
asserted.
5.2.5.7
The SC2200 multiplexes most PCI and Sub-ISA signals on
the balls listed in Table 5-3, in order to reduce the number
of balls on the device. Cycle multiplexing is on a bus-cycle
by bus-cycle basis (see Figure 5-6 on page 161), where the
internal Core Logic PCI bridge arbitrates between PCI
cycles and Sub-ISA cycles. Other PCI and Sub-ISA signals
remain non-shared, however, some Sub-ISA signals may
be muxed with GPIO.
Sub-ISA cycles are only generated as a result of GX1 mod-
ule accesses to the following addresses or conditions:
• ROMCS# address range.
• DOCCS# address range.
• IOCS0# address range.
• IOCS1# address range.
• An I/O write to address 80h or to 84h.
• Internal ISA is programmed to be the subtractive decode
If the Sub-ISA and PCI bus have more than four compo-
nents, the Sub-ISA components can be buffered using
74HCT245 or 74FCT245 type transceivers. The RD# (an
AND of IOR#, MEMR#) signal can be used as DIR control
while TRDE# is used as enable control.
agent and no other agents claim the cycle.
ROM Interface
PCI and Sub-ISA Signal Cycle Multiplexing
000F0000h-000FFFFFh
(Continued)
(64
KB)
and
160
Table 5-3. Cycle Multiplexed PCI / Sub-ISA Balls
DEVSEL#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
TRDY#
STOP#
IRDY#
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
PAR
PCI
Sub-ISA
BHE#
D15
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
D10
D11
D12
D13
D14
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
EBGA
D16
C15
C14
C13
C12
C11
C10
A17
A18
A15
A16
A14
B14
B13
A12
A11
B10
A13
A10
A7
C7
D7
A6
D6
C6
A5
C5
D5
A4
B4
C4
A3
C2
B3
D8
A8
B8
C8
D9
B5
F4
Ball No.
TEPBGA
M2
M4
G1
Revision 3.0
U1
P3
U3
N1
P1
N3
N2
K1
K4
E1
F4
E3
E2
D3
D1
D2
B6
C2
C4
C1
D4
B4
B3
A3
D5
F3
H4
F1
F2
E4
L2
L3
L4
J1
J3
L1
J2
J4