SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 12

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Architecture Overview
GX_BASE+ 8400h-8403h
31:30
28:27
25:24
23:22
20:18
16:8
7:6
Bit
29
26
21
17
5
4
3
2
1
0
Description
MDCTL (MD[63:0] Drive Strength). 11 is strongest, 00 is weakest.
RSVD (Reserved) Write as 0.
MABACTL (MA[12:0] and BA[1:0] Drive Strength). 11 is strongest, 00 is weakest.
RSVD (Reserved). Write as 0.
MEMCTL (RASA#, CASA#, WEA#, CS[1:0]#, CKEA, DQM[7:0] Drive Strength). 11 is strongest, 00 is weakest.
RSVD (Reserved). Write as 0.
RSVD (Reserved). Must be written as 0. Wait state on the X-Bus x_data during read cycles - for debug only.
SDCLKRATE (SDRAM Clock Ratio). Selects SDRAM clock ratio.
000: Reserved
001: ÷ 2
010: ÷ 2.5
011: ÷ 3 (Default)
Ratio does not take effect until the SDCLKSTRT bit (bit 17 of this register) transitions from 0 to 1.
SDCLKSTRT (Start SDCLK). Start operating SDCLK using the new ratio and shift value (selected in bits [20:18] of this reg-
ister).
0: Clear.
1: Enable.
This bit must transition from zero (written to zero) to one (written to one) in order to start SDCLK or to change the shift value.
RFSHRATE (Refresh Interval). This field determines the number of processor core clocks multiplied by 64 between refresh
cycles to the DRAM. By default, the refresh interval is 00h. Refresh is turned off by default.
RFSHSTAG (Refresh Staggering). This field determines number of clocks between the RFSH commands to each of the
four banks during refresh cycles:
00: 0 SDRAM clocks
01: 1 SDRAM clocks (Default)
10: 2 SDRAM clocks
11: 4 SDRAM clocks
Staggering is used to help reduce power spikes during refresh by refreshing one bank at a time. If only one bank is installed,
this field must be written as 00.
2CLKADDR (Two Clock Address Setup). Assert memory address for one extra clock before CS# is asserted.
0: Disable.
1: Enable.
This can be used to compensate for address setup at high frequencies and/or high loads.
RFSHTST (Test Refresh). This bit, when set high, generates a refresh request. This bit is only used for testing purposes.
XBUSARB (X-Bus Round Robin). When enabled, processor, graphics pipeline and non-critical display controller requests
are arbitrated at the same priority level. When disabled, processor requests are arbitrated at a higher priority level. High pri-
ority display controller requests always have the highest arbitration priority.
0: Enable.
1: Disable.
SMM_MAP (SMM Region Mapping). Maps the SMM memory region at GX_BASE+400000 to physical address A0000 to
BFFFF in SDRAM.
0: Disable.
1: Enable.
RSVD (Reserved). Write as 0.
SDRAMPRG (Program SDRAM). When this bit is set, the memory controller will program the SDRAM MRS register using
LTMODE in MC_SYNC_TIM1.
This bit must transition from zero (written to zero) to one (written to one) in order to program the SDRAM devices.
(Continued)
Table 1-2. SC2200 Memory Controller Registers
MC_MEM_CNTRL1 (R/W)
100: ÷ 3.5
101: ÷ 4
110: ÷ 4.5
111: ÷ 5
12
Reset Value: 248C0040h
Revision 3.0