SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 227

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Index CEh
Index CFh
Index D0h
Index D1h-EBh
Index ECh
Index EDh-F3h
Index F4h
The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0].
Reading this register clears the status at both the second and top levels.
A read-only “Mirror” version of this register exists at F0 Index 84h. If the value of the register must be read without clearing the SMI
source (and consequently deasserting SMI), F0 Index 84h can be read instead.
6:0
7:0
7:0
7:3
Bit
7
2
1
0
Description
Memory or I/O Mapped. Determines how User Defined Device 3 is mapped.
0: I/O.
1: Memory.
Mask.
If bit 7 = 0 (I/O):
If bit 7 = 1 (Memory):
Note:
Software SMI. A write to this location generates an SMI. The data written is irrelevant. This register allows software entry
into SMM via normal bus access instructions.
Timer Test Value. The Timer Test register is intended only for test and debug purposes. It is not intended for setting opera-
tional timebases.
Reserved. Reads as 0.
GPWIO2 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO2 pin.
0: No.
1: Yes.
To enable SMI generation:
1) Ensure that GPWIO2 is enabled as an input: F1BAR1+I/O Offset 15h[2] = 0.
2) Set F1BAR1+I/O Offset 15h[6] = 1 to allow SMI generation.
GPWIO1 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO1 pin.
0: No.
1: Yes.
To enable SMI generation:
1) Ensure that GPWIO1 is enabled as an input: F1BAR1+I/O Offset 15h[1] = 0.
2) Set F1BAR1+I/O Offset 15h[5] to 1 to allow SMI generation.
GPWIO0 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO0 pin.
0: No
1: Yes
To enable SMI generation:
1) Ensure that GPWIO0 is enabled as an input: F1BAR1+I/O Offset 15h[0] = 0.
2) Set F1BAR1+I/O Offset 15h[4] to 1 to allow SMI generation.
A "1" in a mask bit means that the address bit is ignored for comparison.
Bit 6
Bit 5
Bits [4:0] Mask for address bits A[4:0]
Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.
(Continued)
0: Disable write cycle tracking
1: Enable write cycle tracking
0: Disable read cycle tracking
1: Enable read cycle tracking
Second Level PME/SMI Status Register 1 (RC)
User Defined Device 3 Control Register (R/W)
Software SMI Register (WO)
Timer Test Register (R/W)
Reserved
Reserved
Reserved
227
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
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