SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 391

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Electrical Specifications
1.
2.
3.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0
1
2
2i
3
4
5
6
6Z
9
RD
A
B
C
t
time or command inactive time. The actual cycle time equals the sum of the command active time and the command
inactive time. The three timing requirements of t
greater than the sum of t
equal to or greater than the value reported in the device’s IDENTIFY DEVICE data.)
This parameter specifies the time from the rising edge of IDE_IOR[0:1]# to the time that the data bus is no longer driven
by the device (TRI-STATE).
The delay from the activation of IDE_IOR[0:1]# or IDE_IOW[0:1]# until the state of IDE_IORDY[0,1] is first sampled. If
IDE_IORDY[0:1] is inactive, then the host waits until IDE_IORDY[0:1] is active before the PIO cycle is completed. If the
device is not driving IDE_IORDY[0:1] negated after activation (t
and t
IDE_IOW[0:1]#, then t
0
is the minimum total cycle time, t
RD
is not applicable. If the device is driving IDE_IORDY[0:1] negated after activation (t
Parameter
Cycle time
Address valid to IDE_IOR[0:1]#/ IDE_IOW[0:1]#
setup (min)
IDE_IOR[0:1]#/IDE_IOW[0:1]# pulse width 8-bit
(min)
IDE_IOR[0:1]#/IDE_IOW[0:1]# recovery time
(min)
IDE_IOW[0:1]# data setup (min)
IDE_IOW[0:1]# data hold (min)
IDE_IOR[0:1]# data setup (min)
IDE_IOR[0:1]# data hold (min)
IDE_IOR[0:1]# data TRI-STATE
IDE_IOR[0:1]#/IDE_IOW[0:1]# to address valid
hold (min)
Read Data Valid to IDE_IORDY[0:1] active (if
IDE_IORDY[0:1] initially low after t
IDE_IORDY[0:1] Setup time
IDE_IORDY[0:1] Pulse Width (max)
IDE_IORDY[0:1] assertion to release (max)
Table 8-24. Register Transfer to/from Device Timing Parameters
1
(min)
RD
2
is met and t
and t
2i
(Continued)
. (This means that a host implementation can lengthen t
2
is the minimum command active time, and t
3
5
is not applicable.
2
(max)
A
(min)
0
, t
2
, and t
1
391
1
2i
are met. The minimum total cycle time requirements is
A
Mode 0
) of IDE_IOR[0:1]# or IDE_IOW[0:1]#, then t
1250
(ns)
600
290
70
60
30
50
30
20
35
5
0
5
-
Mode 1
1250
(ns)
383
290
50
45
20
35
30
15
35
5
0
5
-
2i
is the minimum command recovery
Mode 2
2
1250
(ns)
240
290
30
30
15
20
30
10
35
and/or t
5
0
5
-
A
) of IDE_IOR[0:1]# or
2i
Mode 3
1250
to ensure that t
(ns)
180
30
80
70
20
30
10
35
30
10
5
0
5
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Mode 4
5
1250
(ns)
120
is met
25
70
25
20
10
20
30
10
35
5
0
5
0
is