SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 121

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
SuperI/O Module
Index 00h
Index 01h
Index 02h
Index 03h
Index 04h
Index 05h
Index 06h
Index 07h
Index 08h
Width: Byte
Index 09h
Index 0Ah
This register controls test selection, among other functions. This register cannot be written before reading bit 7 of CRD.
Index 0Bh
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7-0
7:0
6:4
3:0
Bit
7
7
6
Description
Seconds Data. Values may be 00 to 59 in BCD format or 00 to 3B in binary format.
Seconds Alarm Data. Values may be 00 to 59 in BCD format or 00 to 3B in binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected.
Minutes Data. Values can be 00 to 59 in BCD format, or 00 to 3B in binary format.
Minutes Alarm Data. Values can be 00 to 59 in BCD format, or 00 to 3B in binary format.
When bits 7 and 6 are both set to 1, unconditional match is selected. See Section 4.5.2.5 "Alarms" on page 116 for more
information about "unconditional" matches.
Hours Data. For 12-hour mode, values can be 01 to 12 (AM) and 81 to 92 (PM) in BCD format, or 01 to 0C (AM) and 81 to
8C (PM) in binary format. For 24-hour mode, values can be 0- to 23 in BCD format or 00 to 17 in binary format.
Hours Alarm Data. For 12-hour mode, values may be 01 to 12 (AM) and 81 to 92 (PM) in BCD format or 01 to 0C (AM) and
81 to 8C (PM) in Binary format. For 24-hour mode, values may be 0- to 23 in BCD format or 00 to 17 in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected.
Day Of Week Data. Values may be 01 to 07 in BCD format or 01 to 07 in binary format.
Date Of Month Data. Values may be 01 to 31 in BCD format or 01 to 1F in binary format.
Month Data. Values may be 01 to 12 in BCD format or 01 to 0C in binary format.
Year Data. Values may be 00 to 99 in BCD format or 00 to 63 in binary format.
Update in Progress. (RO) This bit is not affected by reset. This bit reads 0 when bit 7 of the CRB Register is 1.
0: Timing registers not updated within 244 s.
1: Timing registers updated within 244 s.
Divider Chain Control. These bits control the configuration of the divider chain for timing generation and register bank
selection. See Table 4-21 on page 123. They are cleared to 000 as long as bit 7 of CRD is 0.
Periodic Interrupt Rate Select. These bits select one of fifteen output taps from the clock divider chain to control the rate of
the periodic interrupt. See Table 4-22 on page 123 and Figure 4-7 on page 115. They are cleared to 000 as long as bit 7 of
CRD is 0.
Set Mode. This bit is reset at V
0: Timing updates occur normally.
1: User copy of time is “frozen”, allowing the time registers to be accessed whether or not an update occurs.
Periodic Interrupt. Bits [3:0] of the CRA Register determine the rate at which this interrupt is generated. It is cleared to 0 on
RTC reset (i.e., hardware or software reset) or when RTC is disable.
0: Disable.
1: Enable.
(Continued)
PP
Seconds Alarm Register - SECA (R/W)
Minutes Alarm Register - MINA (R/W)
Hours Alarm Register - HORA (R/W)
Date of Month Register - DOM (R/W)
RTC Control Register A - CRA (R/W)
RTC Control Register B - CRB (R/W)
power-up reset only.
Day of Week Register - DOW (R/W)
Seconds Register - SEC (R/W)
Table 4-20. RTC Registers
Minutes Register - MIN (R/W)
Month Register - MON (R/W)
Hours Register - HOR (R/W)
Year Register - YER (R/W)
121
Reset Type: Bit Specific
Reset Type: Bit Specific
Reset Type: V
Reset Type: V
Reset Type: V
Reset Type: V
Reset Type: V
Reset Type: V
Reset Type: V
Reset Type: V
Reset Type: V
Reset Type: V
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