SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 397

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Electrical Specifications
1.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
T
T
2CYC
CYC
DS
DH
DVS
DVH
FS
LI
MLI
UI
AZ
ZAH
ZAD
ENV
SR
RFS
RP
IORDYZ
ZIORDY
ACK
SS
t
ent) is waiting for the other agent to respond with a signal before proceeding. t
mum time value. t
UI
, t
MLI
, and t
Parameter
Typical sustained average two cycle time
Two cycle time allowing for clock variations (from rising
edge to next rising edge or from falling edge to next falling
edge of STROBE)
Cycle time allowing for asymmetry and clock variations
(from STROBE edge to STROBE edge)
Data setup time (at recipient)
Data hold time (at recipient)
Data valid setup time at sender (from data bus being valid
until STROBE edge)
Data valid hold time at sender (from STROBE edge until
data may become invalid)
First STROBE time (for device to first negate
IDE_IRDY[0:1] (DSTROBE[0:1]) from IDE_IOW[0:1]#
(STOP[0:1]) during a data in burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output drivers to release (from
being asserted or negated)
Minimum delay time required for output drivers to assert or
negate (from released state)
Envelope time (from IDE_DACK[0:1]# to IDE_IOW[0:1]#
(STOP[0:1]) and IDE_IOR[0:1]# (HDMARDY[0:1]#) during
data out burst initiation)
STROBE to DMARDY time (if DMARDY# is negated before
this long after STROBE edge, the recipient shall receive no
more than one additional data WORD)
Ready-to-final-STROBE time (no STROBE edges shall be
sent this long after negation of DMARDY#)
Ready-to-pause time (time that recipient shall wait to ini-
tiate pause after negating DMARDY#)
Pull-up time before allowing IDE_IORDY[0:1] to be
released
Minimum time device shall wait before driving
IDE_IORDY[0:1]
Setup and hold times for IDE_DACK[0:1]# (before asser-
tion or negation)
Time from STROBE edge to negation of IDE_DREQ[0:1]
or assertion of IDE_IOW[0:1]# (STOP[0:1]) (when sender
terminates a burst)
LI
indicate sender-to-recipient or recipient-to-sender interlocks, that is, one agent (either sender or recipi-
MLI
is a limited time-out with a defined minimum. t
Table 8-27. UltraDMA Data Burst Timing Parameters
1
(Continued)
1
1
397
LI
is a limited time-out with a defined maximum.
Mode 0 (ns)
Min
240
235
114
160
70
20
20
20
20
50
15
5
6
0
0
0
0
0
UI
Max
230
150
10
70
50
75
20
is an unlimited interlock with no maxi-
Mode 1 (ns)
Min
160
156
125
75
10
48
20
20
20
20
50
5
6
0
0
0
0
0
Max
200
150
10
70
30
60
20
Mode 2 (ns)
Min
120
117
100
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55
34
20
20
20
20
50
7
5
6
0
0
0
0
0
Max
170
150
10
70
20
50
20