SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 25

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Signal Definitions
Ball
No.
F1
F2
F3
F4
F28
F29
F30
F31
G1
G2
G3
G4
G28
G29
G30
G31
H1
H2
H3
H4
4, 5
4, 5
Signal Name
IOR#
DOCR#
GPIO14
V
RD#
CLKSEL0
AD23
A23
THRM#
V
V
PWRCNT1
WR#
V
IOW#
DOCW#
GPIO15
ROMCS#
BOOT16
GPWIO1
GPWIO2
V
PWRCNT2
TRDE#
GPIO0
GPIO1
IOCS1#
TFTD12
GPIO20
DOCCS#
TFTD0
GPIO19
INTC#
IOCHRDY
SS
SB
SS
IO
IO
Table 2-2.
(PU/PD)
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PU
(PD
(PD
(PU
(PU
PWR
PWR
PWR
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
22.5
I
I
22.5
I
22.5
22.5
22.5
22.5
22.5
22.5
22.5
22.5
I
22.5
I
22.5
100
100
100
100
(Continued)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
Buffer
IN
IN
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
TS
TS
IN
OD
OD
IN
Type
IN
IN
IN
IN
IN
O
O
IN
IN
IN
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IN
IN
---
STRP
---
---
---
STRP
---
PCI
PCI
PCI
TS1
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
1/4
3/5
3/5
1/4
3/5
TS
TS
Ts
2/14
TS
2/14
TS
TS
TS
TS
T
T
14
14
,
,
,
,
,
,
,
,
,
1
Power
Rail
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
---
---
---
---
---
SB
SB
SB
SB
SB
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Configuration
PMR[21] = 0 and
PMR[2] = 0
PMR[21] = 0 and
PMR[2] = 1
PMR[21] = 1 and
PMR[2] = 1
---
---
Strap (See Table 2-
6 on page 51.)
Cycle Multiplexed
---
---
---
---
---
PMR[21] = 0 and
PMR[2] = 0
PMR[21] = 0 and
PMR[2] = 1
PMR[21] = 1 and
PMR[2] = 1
---
Strap (See Table 2-
6 on page 51.)
---
---
---
---
PMR[12] = 0
PMR[12] = 1
PMR[23]
PMR[13] = 0
PMR[23]
PMR[13] = 1
PMR[23]
PMR[23]
PMR[7] = 0
PMR[23]
PMR[7] = 1
PMR[23]
PMR[9] = 0 and
PMR[4] = 0
PMR[9] = 0 and
PMR[4] = 1
PMR[9] = 1 and
PMR[4] = 1
3
3
3
3
3
3
= 0 and
= 0 and
= 1
= 0 and
= 0 and
= 1
25
Ball
No.
H28
H29
H30
H31
J1
J2
J3
J4
J28
J29
J30
J31
K1
K2
K3
K4
K28
K29
K30
K31
L1
L2
L3
L4
L28
L29
L30
L31
M1
M2
M3
4
4
4
4
4
4
4
Signal Name
V
CLK32
GPIO11
RI2#
IRQ15
SDATA_IN2
HSYNC
VSYNC
IRTX
SOUT3
GPIO17
IOCS0#
TFTDCK
IRRX1
SIN3
POR#
MD0
MD1
RED
V
V
V
V
MD2
MD3
MD4
AV
V
AV
V
V
MD5
V
MD6
AV
V
GREEN
SBL
SSCRT
CCCRT
SS
SS
SS
CORE
CORE
SS
IO
SSCRT
CCCRT
CCCRT
(PU/PD)
(PU
(PU
(PU
(PU
(PU
(PU
PWR
GND
PWR
GND
GND
GND
GND
PWR
PWR
PWR
GND
PWR
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
22.5
I
22.5
I
22.5
I
22.5
22.5
22.5
I
I
I
)
)
)
)
)
)
Buffer
WIRE
WIRE
IN
TS
TS
TS
TS
TS
TS
TS
Type
IN
IN
IN
IN
IN
IN
IN
O
O
O
O
O
O
O
O
O
IN
IN
IN
IN
IN
IN
IN
---
---
---
---
---
---
---
---
---
---
---
---
---
TS1
2/5
TS
8/8
1/4
1/4
8/8
8/8
TS
3/5
3/5
1/4
TS
TS
TS
TS
TS
2/5
2/5
2/5
2/5
2/5
2/5
2/5
T
T
T
T
T
T
T
,
,
,
,
,
,
,
,
,
1
Power
AV
CCRT
AV
CCRT
Rail
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
---
---
---
---
---
---
---
---
---
---
---
---
---
SB
SB
SB
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
C-
C-
Configuration
---
---
PMR[18] = 0 and
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
PMR[18] = 0 and
PMR[8] = 1
F3BAR0+Memory
Offset 08h[21] = 1
---
---
PMR[6] = 0
PMR[6] = 1
PMR[23]
PMR[5] = 0
PMR[23]
PMR[5] = 1
PMR[23]
PMR[6] = 0
PMR[6] =1
---
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3
3
3
= 0 and
= 0 and
= 1