SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 13

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Architecture Overview
GX_BASE+8404h-8407h
GX_BASE+8408h-840Bh
31:14
13:12
31:16
10:8
5:3
Bit
11
10
15
14
13
12
11
9
8
7
6
2
1
0
7
Description
RSVD (Reserved). Write as 0.
SDCLKCTL (SDCLK High Drive/Slew Control). Controls the high drive and slew rate of SDCLK[3:0] and SDCLK_OUT.
11 is strongest, 00 is weakest.
RSVD (Reserved). Write as 0.
SDCLKOMSK# (Enable SDCLK_OUT). Turns on the output.
0: Enable.
1: Disable.
SDCLK3MSK# (Enable SDCLK3). Turns on the output.
0: Enable.
1: Disable.
SDCLK2MSK# (Enable SDCLK2). Turns on the output.
0: Enable.
1: Disable.
SDCLK1MSK# (Enable SDCLK1). Turns on the output. 0
0: Enable.
1: Disable.
SDCLK0MSK# (Enable SDCLK0). Turns on the output.
0: Enable.
1: Disable.
SHFTSDCLK (Shift SDCLK). This function allows shifting SDCLK to meet SDRAM setup and hold time requirements. The
shift function will not take effect until the SDCLKSTRT bit (bit 17 of MC_MEM_CNTRL1) transitions from 0 to 1:
000: No shift
001: Shift 0.5 core clock
010: Shift 1 core clock
011: Shift 1.5 core clock
RSVD (Reserved). Write as 0.
RD (Read Data Phase). Selects if read data is latched one or two core clock after the rising edge of SDCLK.
1: 2 Core clocks.
FSTRDMSK (Fast Read Mask). Do not allow core reads to bypass the request FIFO.
0: Disable.
1: Enable.
RSVD (Reserved). Write as 0070h
RSVD (Reserved). Write as 0.
SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1). Selects number of module banks installed per SODIMM
for SODIMM:
0: 1 Module bank (Bank 0 only)
1: 2 Module banks (Bank 0 and 1)
RSVD (Reserved). Write as 0.
SODIMM_COMP_BNK (SODIMM Component Banks - Banks 0 and 1). Selects the number of component banks per
module bank for SODIMM:
0: 2 Component banks
1: 4 Component banks
Banks 0 and 1 must have the same number of component banks.
RSVD (Reserved). Write as 0.
SODIMM_SZ (SODIMM Size - Banks 0 and 1). Selects the size of SODIMM:
000: 4 MB
001: 8 MB
This size is the total of both banks 0 and 1. Also, banks 0 and 1 must be the same size.
RSVD (Reserved). Write as 0.
0: 1 Core clock.
Table 1-2. SC2200 Memory Controller Registers (Continued)
010: 16 MB
011: 32 MB
(Continued)
MC_MEM_CNTRL2 (R/W)
100: 64 MB
101: 128 MB
MC_BANK_CFG (R/W)
100: Shift 2 core clocks
101: Shift 2.5 core clocks
110: Shift 3 core clocks
111: Reserved
13
110: 256 MB
111: 512 MB
Reset Value: 00000801h
Reset Value: 41104110h
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