SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 170

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

www.national.com
Core Logic Module
will remain active after POR#. Therefore, BIOS must
ensure that ACPI is inactive before GPIO63 is pulsed low.
Power Button Wake Event - Detection of a high-to-low
transition on the debounced PWRBTN# input signal when
in SL1 to SL5 Sleep states. The system is considered in
the Sleep state, only after it actually transitioned into the
state and not only according to the SLP_TYP field.
In reaction to this event, the PWRBTN_STS bit
(F1BAR1+I/O Offset 08h[8]) is set to 1 and a wakeup event
or an interrupt is generated (note that this is regardless of
the PWRBTN_EN bit, F1BAR1+I/O Offset 0Ah[8]).
Power Button Sleep Event - Detection of a high-to-low
transition on the debounced PWRBTN# input signal, when
in the Working state (S0).
In reaction to this event, the PWRBTN_STS bit is set to 1.
• When both the PWRBTN_STS bit and the
• When SCI_EN bit is 0, ONCTL# and PWRCNT[2:1] are
Power Button Override
When PWRBTN# is 0 for more than four seconds, ONCTL#
and PWRCNT[2:1] are deasserted (i.e., the system transi-
tions to the SL5 state, "Soft Off"). This power management
event is called the power button override event.
In reaction to this event, the PWRBTN_STS bit is cleared
to 0 and the PWRBTNOR_STS bit (F1BAR1+I/O Offset
08h[11]) is set to 1.
Thermal Monitoring
The thermal monitoring event (THRM#) enables control of
ACPI-OS Control.
When the THRM# signal transitions from high-to-low, the
THRM_STS bit (F1BAR1+I/O Offset 10h[5]) is set to 1. If
the THRM_EN bit (F1BAR1+I/O Offset 12h[5]) is also set
to 1, an interrupt is generated.
SDATA_IN2, IRRX1, RI2#
Section 4.4.1 "SIO Control and Configuration Registers" on
page 106 for control and operation.
5.2.9.5
• During initialization, the BIOS should:
• SMM code should clear the CLK_STP bit in the PM
PWRBTN_EN bit are set to 1, an SCI interrupt is gener-
ated.
deasserted immediately regardless of the PWRBTN_EN
bit.
— Clear the SUSP_HLT bit in CCR2 (GX1 module,
— Disable the SUSP_3V option in C3 power state (F0
— Disable the SUSP_3V option in SL1 sleep state (F0
Clock Stop Control register (GX_BASE+Memory Offset
8500h[0]) to 0 when entering C3 state.
Index C2h[3]) to 0. This is needed for compliance
with C0 definition of ACPI, when the Halt Instruction
(HLT) is executed.
Index 60h[2]).
Index 60h[1]).
Usage Hints
(Continued)
170
• SMM code should correctly set the CLK_STP bit in the
5.2.10 Power Management Programming
The power management resources provided by a com-
bined GX1 module and Core Logic module based system
supports a high efficiency power management implementa-
tion. The following explanations pertain to a full-featured
“notebook” power management system. The extent to
which these resources are employed depends on the appli-
cation and on the discretion of the system designer.
Power management resources can be grouped according
to the function they enable or support. The major functions
are as follows:
• APM Support
• CPU Power Management
• Peripheral Power Management
Included in the following subsections are details regarding
the registers used for configuring power management fea-
tures. The majority of these registers are directly accessed
through the PCI configuration register space designated as
Function 0 (F0). However, included in the discussions are
references to F1BARx+I/O Offset xxh. This refers to regis-
ters accessed through base address registers in Function 1
(F1) at Index 10h (F1BAR0) and Index 40h (F1BAR1).
5.2.10.1 APM Support
Many notebook computers rely solely on an Advanced
Power Management (APM) driver for enabling the operat-
ing system to power-manage the CPU. APM provides sev-
eral
management; but in its current form, APM is imperfect for
the following reasons:
• APM is an OS-specific driver, and may not be available
• Application support is inconsistent. Some applications in
• APM does not help with Suspend determination or
The Core Logic module provides two entry points for APM
support:
• Software CPU Suspend control via the CPU Suspend
• Software SMI entry via the Software SMI register (F0
PM Clock Stop Control register (GX_BASE+Memory
Offset 8500h[0]) when entering the SL1, SL2, and SL3
states.
— Suspend Modulation
— 3V Suspend
— Save-to-Disk
— Device Idle Timers and Traps
— General Purpose Timers
— ACPI Timer Register
— Power Management SMI Status Reporting Registers
for some operating systems.
foreground may prevent Idle calls.
peripheral power management.
Command register (F0 Index AEh)
Index D0h). This allows the APM BIOS to be part of the
SMI handler.
services
which
enhance
the
system
Revision 3.0
power