SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 181

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Core Logic Module
Fast Path Write captures the data and address bit 1 (A1) of
the first access, but does not generate an SMI. A1 is stored
in F3BAR0+Memory Offset 14h[15]. The second access
causes an SMI, and the data and address are captured as
in a normal trapped I/O.
GX1
Module
Core Logic Module
F1BAR0+Memory
top-level source
Read to Clear
AUDIO_SMI
to determine
Other_SMI
Other_SMI
Top Level
SMI# Asserted
Offset 02h
Bits [15:2]
of SMI
Bit 1
Bit 0
If bit 1 = 1,
Source of
SMI is
Audio Event
(Continued)
SMI Deasserted after all SMI Sources are Cleared
(i.e., Top, Second, and Third Levels)
(External SMI)
If Bit X = 1
Figure 5-14. Audio SMI Tree Example
SMM software reads SMI Header
F3BAR0+Memory
SER_INTR_SMI
I/O_TRAP_SMI
Second Level
Read to Clear
source of SMI
to determine
second-level
ABM5_SMI
ABM4_SMI
ABM3_SMI
ABM2_SMI
ABM1_SMI
ABM0_SMI
Offset 10h
Bits [15:8]
RSVD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
181
In Fast Path Write, the Core Logic module responds to
writes to the following addresses:
Table 5-38 on page 269 shows the bit formats of the sec-
ond level SMI status reporting registers and the Fast Path
Read/Write programming bits.
Take
Appropriate
Action
If bit 0 = 1,
Source of
SMI is
I/O Trap
388h, 38Ah, 38Bh, 2x0h, 2x2h, and 2x8h
If Bit X = 0
(Internal SMI)
SMI_SC/FM_TRAP
SMI_SC/FM_TRAP
F3BAR0+Memory
SMI_DMA_TRAP
SMI_MPU_TRAP
Read to Clear
source of SMI
to determine
Third Level
Bits [31:14]
Offset 14h
Other_RO
Other_RO
third-level
Bits [9:0]
Call internal SMI handler
to take appropriate action
Bit 13
Bit 12
Bit 11
Bit 10
Take
Appropriate
Action
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