SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 354

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Video Processor Module
Offset 0Ch-0Fh
Offset 10h-13h
Offset 14h-17h
Offset 18h-1Bh
Offset 1Ch-1Fh
Offset 20h-23h
This register specifies the base address in graphics memory where odd video field data are stored. Changes to this register take effect
at the beginning of the next field. The value in this register is 16-byte aligned.
Note:
Offset 24h-27h
This register specifies the base address in graphics memory where even video field data are stored. Changes to this register take effect
at the beginning of the next field. The value in this register is 16-byte aligned.
Note:
Offset 28h-2Bh
This register specifies the logical width of the video data buffer. This value is added to the start of the line address to get the address of
the next line where video data are stored to memory. This value must be an integral number of DWORDs.
Offset 2Ch-3Fh
Offset 40h-43h
This register specifies the base address in graphics memory where VBI data for odd fields are stored. Changes to this register take
effect at the beginning of the next field. The value in this register is 16-byte aligned.
Note:
31:10
31:10
31:16
31:0
31:0
15:0
31:0
7:1
9:0
9:0
Bit
0
This register is double-buffered. When a new value is written to this register, the new value is placed in a special "pending" reg-
ister, and the "Base Register Not Updated" bit (F4BAR2+MemoryOffset 08h[21]) is set to 1. The Video Data Odd Base register
(this register) is not updated at this point. When the first data of the next field is stored to memory, the pending values of all
base registers (including this one) are written to the appropriate base registers, and the "Base Register Not Updated" bit is
cleared.
This register is double-buffered. When a new value is written to this register, the new value is placed in a special "pending" reg-
ister, and the "Base Register Not Updated" bit (F4BAR2+MemoryOffset 08h[21]) is set to 1. The Video Data Even Base register
(this register) is not updated at this point. When the first data of the next field is stored to memory, the pending values of all
base registers (including this one) are written to the appropriate base registers, and the "Base Register Not Updated" bit is
cleared.
This register is double-buffered. When a new value is written this register, the new value is placed in a special "pending" regis-
ter, and the "Base Register Not Updated" bit (F4BAR2+MemoryOffset 08h[21]) is set to 1. The VBI Data Odd Base Register
(this register) is not updated at this point. When the first data of the next field is stored to memory, the pending values of all
base registers (including this one) are written to the appropriate base registers, and the "Base Register Not Updated" bit is
cleared.
Description
Reserved. (Read Only)
Run Status. (Read Only)
0: Video port capture is not active.
1: Video port capture is in progress.
Reserved.
Current Line. Indicates the video line currently being stored to memory. The count indicated in this field is reset to 0 at the
start of each field.
Reserved. Must be set to 0.
Line Target. Indicates the video line to generate an interrupt on.
Video Odd Base Address. Base address where odd video data are stored in graphics memory. Bits [3:0] are always 0, and
define the required address space.
Video Even Base Address. Base address where even video data are stored in graphics memory. Bits [3:0] are always 0,
and define the required address space.
Reserved.
Video Data Pitch. Specifies the logical width of the video data buffer. Bits [1:0] are always 0.
VBI Odd Base Address. Base address where VBI data for odd fields is stored in graphics memory. Bits [3:0] are always 0
and define the required address space.
Table 6-8. F4BAR2+Memory Offset: VIP Configuration Registers (Continued)
(Continued)
Video Data Even Base Register (R/W)
Video Data Odd Base Register (R/W)
VBI Data Odd Base Register (R/W)
Video Current Line Register (RO)
Video Line Target Register (R/W)
Video Data Pitch Register (R/W)
Reserved
Reserved
Reserved
Reserved
354
Reset Value: xxxxxxxxh
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00h
Revision 3.0