SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 66

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Signal Definitions
2.4.7
Signal Name
A[23:0]
D15
D14
D13
D12
D11
D10
D9
D8
D[7:0]
BHE#
IOCS1#
IOCS0#
ROMCS#
DOCCS#
TRDE#
RD#
WR#
IOR#
IOW#
DOCR#
DOCW#
Sub-ISA Interface Signals
Table 2-3
Table 2-3
on page
on page
EBGA
AL12
AJ13
See
See
32.
32.
G4
G1
G3
G3
B5
H2
H3
H1
J4
F3
F1
F1
(Continued)
Ball No.
TEPBGA
Table 2-5
Table 2-5
on page
on page
D10
N30
A10
C30
N31
D11
See
See
47.
47.
D9
D9
E4
A9
B8
B9
A8
A8
Type
I/O
O
O
O
O
O
O
O
O
O
O
O
O
Description
Address Lines
Data Bus
Byte High Enable. With A0, defines byte
accessed for 16 bit wide bus cycles.
I/O Chip Selects
ROM or Flash ROM Chip Select
DiskOnChip or NAND Flash Chip Select
Transceiver Data Enable Control. Active
low for Sub-ISA data transfers. The signal
timing is as follows:
• In a read cycle, TRDE# has the same
• In a write cycle, TRDE# is asserted (to
Memory or I/O Read. Active on any read
cycle.
Memory or I/O Write. Active on any write
cycle.
I/O Read. Active on any I/O read cycle.
I/O Write. Active on any I/O write cycle.
DiskOnChip or NAND Flash Read. Active
on any memory read cycle to DiskOnChip.
DiskOnChip or NAND Flash Write. Active
on any memory write cycle to DiskOnChip.
timing as RD#.
active low) at the time WR# is asserted. It
continues being asserted for one PCI
clock cycle after WR# has been negated,
then it is negated.
66
GPIO17+TFTDCK
DOCW#+GPIO15
CLKSEL0 (Strap)
DOCR#+GPIO14
GPIO1+TFTD12
BOOT16 (Strap)
GPIO20+TFTD0
AB1C+GPIO20
IOW#+GPIO15
IOR#+GPIO14
AB1D+GPIO1
AD[31:24]
DEVSEL#
AD[23:0]
C/BE3#
C/BE2#
C/BE1#
C/BE0#
STOP#
TRDY#
GPIO0
IRDY#
Mux
PAR
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Revision 3.0