SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 213

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
6
5
4
3
2
1
Description
User Defined Device 3 (UDEF3) Access Trap. If this bit is enabled and an access occurs in the programmed address
range, an SMI is generated. UDEF3 address programming is at F0 Index C8h (Base Address register) and CEh (Control
register).
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[4].
User Defined Device 2 (UDEF2) Access Trap. If this bit is enabled and an access occurs in the programmed address
range, an SMI is generated. UDEF2 address programming is at F0 Index C4h (Base Address register) and CDh (Control
register).
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[3].
User Defined Device 1 (UDEF1) Access Trap. If this bit is enabled and an access occurs in the programmed address
range, an SMI is generated. UDEF1 address programming is at F0 Index C0h (base address register), and CCh (control
register).
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[2].
Keyboard/Mouse Access Trap.
0: Disable.
1: Enable.
If this bit is enabled and an access occurs in the address ranges listed below, an SMI is generated.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[3].
Parallel/Serial Access Trap.
0: Disable.
1: Enable.
If this bit is enabled and an access occurs in the address ranges listed below, an SMI is generated.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[2].
Floppy Disk Access Trap.
0: Disable.
1: Enable.
If this bit is enabled and an access occurs in the address ranges listed below, an SMI is generated.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[1].
— Keyboard Controller: I/O Ports 060h/064h.
— COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included).
— COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included).
— LPT1: I/O Port 3BCh-3BEh.
— LPT2: I/O Port 378h-37Fh.
— COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded).
— COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded).
— COM3: I/O Port 3E8h-3EFh.
— COM4: I/O Port 2E8h-2EFh.
— Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h.
— Secondary floppy disk: I/O Port 372h-375h, 377h.
(Continued)
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