SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 65

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Signal Definitions
2.4.6
Signal Name
SERR#
REQ1#
REQ0#
GNT1#
GNT0#
PCI Bus Interface Signals (Continued)
EBGA
A9
E3
C1
D2
D4
(Continued)
BalL No.
TEPBGA
H1
C6
C5
A5
B5
Type
I/O
O
I
Description
System Error. SERR# can be asserted by
any agent for reporting errors other than PCI
parity, so that the PCI central agent notifies
the processor. When the Parity Enable bit is
set in the Memory Controller Configuration
register, SERR# is asserted upon detection
of a parity error in read operations from
DRAM.
This signal is internally connected to a pull-
up resistor.
Request Lines. REQ[1:0]# indicate to the
arbiter that an agent requires the bus. Each
master has its own REQ# line. REQ# priori-
ties (in order) are:
1)
2)
3)
4)
5)
6)
7)
Each REQ# is internally connected to a pull-
up resistor.
Grant Lines. GNT[1:0]# indicate to the
requesting master that it has been granted
access to the bus. Each master has its own
GNT# line. GNT# can be retracted at any
time a higher REQ# is received or if the mas-
ter does not begin a cycle within a minimum
period of time (16 PCI clocks).
Each of these signals is internally connected
to a pull-up resistor.
K and GNT1# must have a pull-down resis-
tor of 1.5 K .
GNT0# must have a pull-up resistor of 1.5
VIP
IDE Channel 0
IDE Channel 1
Audio
USB
External REQ0#
External REQ1#.
65
DID1 (Strap)
DID0 (Strap)
www.national.com
Mux
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