SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 223

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Index A6h-A7h
Index A8h-A9h
Index AAh-ABh
Index ACh-ADh
Index AEh
Index AFh
Index B0h-B3h
Index B4h
Index B5h
15:0
15:0
15:0
7:0
7:0
7:0
7:0
Bit
Description
Video Idle Timer Count. This idle timer determines when the graphics subsystem has been idle as part of the Suspend-
determination algorithm. The 16-bit value programmed in this register represents the period of video inactivity after which
the system is alerted via an SMI. The count in this timer is automatically reset at any access to the graphics controller
space.
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[7] = 1.
Since the graphics controller is embedded in the GX1 module, video activity is communicated to the Core Logic module via
the serial connection (PSERIAL register, bit 0). The Core Logic module also detects accesses to standard VGA space on
PCI (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) if an external VGA controller is being used.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[7].
Video Overflow Count. Each time the video speedup counter is triggered, a 100 msec timer is started. If the 100 msec
timer expires before the video speedup counter lapses, the Video Overflow Count register increments and the 100 msec
timer retriggers. Software clears the overflow register when new evaluations are to begin. The count contained in this regis-
ter can be combined with other data to determine the type of video accesses present in the system.
Secondary Hard Disk Idle Timer Count. This idle timer is used to determine when the secondary hard disk is not in use so
that it can be powered down. The 16-bit value programmed in this register represents the period of hard disk inactivity after
which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs
to the configured hard disk’s data port (I/O port 1F0h or 170h).
This counter uses a 1 second timebase. To enable this timer, set F0 Index 83h[7] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[4].
Software CPU Suspend Command. If bit 0 in the Clock Stop Control register is set low (F0 Index BCh[0] = 0), a write to
this register causes an internal SUSP#/SUSPA# handshake with the GX1 module, placing the GX1 module in a low-power
state. The actual data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the GX1 module halt con-
dition.
If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the internal SUSP_3V signal is
asserted after the SUSP#/SUSPA# halt. Upon a Resume event, the PLL delay programmed in the F0 Index BCh[7:4] is
invoked, allowing the clock chip and GX1 module PLL to stabilize before deasserting SUSP#.
Software CPU Stop Clock Suspend. A write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing
the GX1 module in a low-power state. Following this handshake, the SUSP_3V signal is asserted. The SUSP_3V signal is
intended to be used to stop all system clocks.
Upon a Resume event, the internal SUSP_3V signal is deasserted. After a slight delay, the Core Logic module deasserts
the SUSP# signal. Once the clocks are stable, the GX1 module deasserts SUSPA# and system operation resumes.
Floppy Port 3F2h Shadow. Last written value of I/O Port 3F2h. Required for support of FDC power On/Off and 0V Sus-
pend/Resume coherency.
This register is a copy of an I/O register which cannot safely be directly read. The value in this register is not deterministic of
when the register is being read. It is provided here to assist in a Suspend-to-Disk operation.
Floppy Port 3F7h Shadow. Last written value of I/O Port 3F7h. Required for support of FDC power On/Off and 0V Sus-
pend/Resume coherency.
This register is a copy of an I/O register which cannot safely be directly read. The value in this register is not deterministic of
when the register is being read. It is provided here to assist in a Suspend-to-Disk operation.
(Continued)
Secondary Hard Disk Idle Timer Count Register (R/W)
Suspend Notebook Command Register (WO)
Floppy Port 3F2h Shadow Register (RO)
Floppy Port 3F7h Shadow Register (RO)
CPU Suspend Command Register (WO)
Video Idle Timer Count Register (R/W)
Video Overflow Count Register (R/W)
Reserved
Reserved
223
Reset Value: 0000h
Reset Value: 0000h
Reset Value: 0000h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: xxh
Reset Value: xxh
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