SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 185

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Core Logic Module
5.3.2
The tables in this subsection summarize the registers of
the Core Logic module. Included in the tables are the regis-
ter’s reset values and page references where the bit for-
mats are found.
00h-01h
02h-03h
04h-05h
06h-07h
08h
09h-0Bh
0Ch
0Dh
0Eh
0Fh
10h-13h
14h-17h
18h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48h-4Bh
4Ch-4Fh
50h
51h
52h
53h
54h-59h
5Ah
5Bh
5Ch
5Dh
5Eh-5Fh
60h-63h
64h-6Dh
6Eh-6Fh
F0 Index
Register Summary
Width
(Bits)
32
32
16
16
16
16
24
---
16
16
---
---
---
---
32
---
---
32
---
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Table 5-14. F0: PCI Header and Bridge Configuration Registers
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
---
---
---
---
---
---
---
---
(Continued)
Name
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
Base Address Register 0 (F0BAR0) — Sets the base address for
the I/O mapped GPIO Runtime and Configuration Registers (sum-
marized in Table 5-15).
Base Address Register 1 (F0BAR1) — Sets the base address for
the I/O mapped LPC Configuration Registers (summarized in
Table 5-16)
Reserved
Subsystem Vendor ID
Subsystem ID
Reserved
PCI Function Control Register 1
PCI Function Control Register 2
Reserved
PIT Delayed Transactions Register
Reset Control Register
Reserved
PCI Functions Enable Register
Miscellaneous Enable Register
Reserved
Top of System Memory
PIT Control/ISA CLK Divider
ISA I/O Recovery Control Register
ROM/AT Logic Control Register
Alternate CPU Support Register
Reserved
Decode Control Register 1
Decode Control Register 2
PCI Interrupt Steering Register 1
PCI Interrupt Steering Register 2
Reserved
ACPI Control Register
Reserved
ROM Mask Register
for GPIO and LPC Support Summary
185
Note:
Function 4 (F4) is for Video Processor support
(although accessed through the Core Logic PCI
configuration registers). Refer to Section 6.3.1
"Register Summary" on page 334 for details.
FFFFFFFFh
00000001h
00000001h
00000000h
060100h
FFF0h
100Bh
0500h
000Fh
0280h
100Bh
0500h
Reset
Value
FEh
7Bh
00h
00h
00h
80h
00h
00h
00h
39h
00h
00h
02h
01h
00h
00h
00h
40h
98h
00h
00h
01h
20h
00h
00h
00h
00h
www.national.com
(Table 5-29)
Reference
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