SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 63

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
Signal Definitions
2.4.6
Signal Name
TRDY#
STOP#
PCI Bus Interface Signals (Continued)
EBGA
B8
D9
(Continued)
BalL No.
TEPBGA
G1
F1
Type
I/O
I/O
Description
Target Ready. TRDY# is asserted to indicate
that the target agent is able to complete the
current data phase of the transaction. TRDY#
is used in conjunction with IRDY#. A data
phase is complete on any PCI clock in which
both TRDY# and IRDY# are sampled as
asserted. During a read, TRDY# indicates
that valid data is present on AD[31:0]. During
a write, it indicates that the target is prepared
to accept data. Wait cycles are inserted until
both IRDY# and TRDY# are asserted
together.
This signal is internally connected to a pull-
up resistor.
Target Stop. STOP# is asserted to indicate
that the current target is requesting that the
master stop the current transaction. This sig-
nal is used with DEVSEL# to indicate retry,
disconnect, or target abort. If STOP# is sam-
pled active by the master, FRAME# is deas-
serted and the cycle is stopped within three
PCI clock cycles. As an input, STOP# can be
asserted in the following cases:
1)
2)
3)
This signal is internally connected to a pull-
up resistor.
If a PCI master tries to access memory
that has been locked by another master.
This condition is detected if FRAME#
and LOCK# are asserted during an
address phase.
If the PCI write buffers are full or if a pre-
viously buffered cycle has not com-
pleted.
On read cycles that cross cache line
boundaries. This is conditional based
upon the programming of GX1 module’s
PCI
41h[1].
63
Configuration
Register,
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Mux
D13
D15