SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 356

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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7.0
7.1
The Test Access Port (TAP) allows board level interconnec-
tion verification and chip production tests. An IEEE-
1149.1a compliant test interface, TAP supports all IEEE
mandatory instructions as well as several optional instruc-
tions for added functionality. See Table 7-1 for a summary
of all instructions support. For further information on JTAG,
refer to IEEE Standard 1149.1a-1993 Test Access Port and
Boundary-Scan Architecture.
7.1.1
The TAP supports all IEEE mandatory instructions, includ-
ing:
• BYPASS
• EXTEST
• SAMPLE/PRELOAD
Presents the shortest path through a given chip (a 1-bit
shift register).
Drives data loaded into the JTAG path (possibly with a
SAMPLE/PRELOAD instruction) to output pins.
Captures chip inputs and outputs.
TESTABILITY (JTAG)
Code
000
001
010
011
100
101
110
111
Debugging and Monitoring
Mandatory Instruction Support
SAMPLE/PRELOAD
Instruction
Reserved
Reserved
EXTEST
IDCODE
BYPASS
CLAMP
HIZ
Table 7-1. JTAG Mode Instruction Support
Activity
Drives shifted data to output pins.
Captures inputs and system outputs.
Scans out device identifier.
Puts all output and bidirectional pins in TRI-STATE mode.
Drives fixed data from Boundary Scan register.
Presents shortest external path through device.
356
7.1.2
The TAP supports the following IEEE optional instructions:
• IDCODE
• CLAMP
• HIZ
7.1.3
Balls that are not part of the JTAG chain:
• CRT DACs
• USB I/Os
Presents the contents of the Device Identification
register in serial format.
Ensures that the Bypass register is connected between
TDI and TDO, and then drives data that was loaded into
the Boundary Scan register (e.g., via SAMPLE-
PRELOAD instruction) to output signals. These signals
do not change while the CLAMP instruction is selected.
(including all pins that do not require a TRI-STATE
output for normal functionality). Note that not all pull-up
resistors are disabled in this state.
Puts all chip outputs in inactive (floating) state
Optional Instruction Support
JTAG Chain
Revision 3.0