SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 264

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
Index 44h-47h
The structure of this register depends on the value of bit 20.
If bit 20 = 0, Multiword DMA
Settings for a Fast-PCI clock frequency of 33.3 MHz:
Settings for a Fast-PCI clock frequency of 48 MHz:
Settings for a Fast-PCI clock frequency of 66.7 MHz:
Note:
If bit 20 = 1, UltraDMA
Settings for a Fast-PCI clock frequency of 33.3 MHz:
Settings for a Fast-PCI clock frequency of 48 MHz:
Settings for a Fast-PCI clock frequency of 66.7 MHz:
Note:
Table 5-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration (Continued)
30:21
19:16
15:12
30:24
23:21
19:16
15:12
11:8
11:8
— Multiword DMA Mode 0 = 00077771h
— Multiword DMA Mode 1 = 00012121h
— Multiword DMA Mode 2 = 00002020h
— Multiword DMA Mode 0 = 000BBBB2h
— Multiword DMA Mode 1 = 00024241h
— Multiword DMA Mode 2 = 00013131h
— Multiword DMA Mode 0 = 000FFFF3h
— Multiword DMA Mode 1 = 00035352h
— Multiword DMA Mode 2 = 00015151h
— UltraDMA Mode 0 = 00921250h
— UltraDMA Mode 1 = 00911140h
— UltraDMA Mode 2 = 00911030h
— UltraDMA Mode 0 = 00932470h
— UltraDMA Mode 1 = 00922260h
— UltraDMA Mode 2 = 00922140h
— UltraDMA Mode 0 = 009436A1h
— UltraDMA Mode 1 = 00933481h
— UltraDMA Mode 2 = 00923261h
7:4
3:0
7:4
3:0
Bit
31
20
31
20
All references to "cycle" in the following bit descriptions are to a Fast-PCI clock cycle.
All references to "cycle" in the following bit descriptions are to a Fast-PCI clock cycle.
Description
PIO Mode Format. This bit sets the PIO mode format for all channels and drives. Bit 31 of Offsets 2Ch, 34h, and 3Ch are
R/W, but have no function so are defined as reserved.
0: Format 0.
1 Format 1.
Reserved. Must be set to 0.
DMA Select. Selects type of DMA operation. 0: Multiword DMA
tKR. IDE_IOR# recovery time (4-bit) (value + 1 cycle).
tDR. IDE_IOR# pulse width (value + 1 cycle).
tKW. IDE_IOW# recovery time (4-bit) (value + 1 cycle).
tDW. IDE_IOW# pulse width (value + 1 cycle).
tM. IDE_CS[1:0]# to IDE_IOR#/IOW# setup; IDE_CS[1:0]# setup to IDE_DACK0#/DACK1#.
PIO Mode Format. This bit sets the PIO mode format for all channels and drives. Bit 31 of Offsets 2Ch, 34h, and 3Ch are
R/W, but have no function so are defined as reserved.
0: Format 0
1: Format 1
Reserved. Must be set to 0.
BSIZE. Input buffer threshold.
DMA Select. Selects type of DMA operation. 1: UltraDMA.
tCRC. CRC setup UDMA in IDE_DACK# (value + 1 cycle) (for host terminate CRC setup = tMLI + tSS).
tSS. UDMA out (value + 1 cycle).
tCYC. Data setup and cycle time UDMA out (value + 2 cycles).
tRP. Ready to pause time (value + 1 cycle). Note: tRFS + 1 tRP on next clock.
tACK. IDE_CS[1:0]# setup to IDE_DACK0#/DACK1# (value + 1 cycle).
(Continued)
Channel 0 Drive 0 DMA Control Register (R/W)
264
Reset Value: 00077771h
Revision 3.0