SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 345

no-image

SC2200

Manufacturer Part Number
SC2200
Description
Thin Client On a Chip
Manufacturer
NSC [National Semiconductor]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC2200A-00
Manufacturer:
MAXIM/美信
Quantity:
20 000
Part Number:
SC2200A-00A00
Manufacturer:
MAXIM
Quantity:
15
Part Number:
SC2200A-00A00E
0
Part Number:
SC2200UCL-26
Manufacturer:
ALTERA
0
Part Number:
SC2200UCL-266
Manufacturer:
NSC
Quantity:
5 510
Part Number:
SC2200UCL-266
Manufacturer:
AMD
Quantity:
648
Part Number:
SC2200UCL-266
Manufacturer:
NS/国半
Quantity:
20 000
Part Number:
SC2200UCL-266 D2
Manufacturer:
NS/国半
Quantity:
20 000
Part Number:
SC2200UFH-266
Manufacturer:
SIERRA
Quantity:
1 238
Part Number:
SC2200UFH-266
Manufacturer:
AMD
Quantity:
996
Part Number:
SC2200UFH-266
Manufacturer:
NS/国半
Quantity:
20 000
Revision 3.0
Video Processor Module
Offset 48h-4Bh
Offset 4Ch-4Fh
31:16
31:22
21:20
19:18
17:16
15:14
15:8
7:0
Bit
13
2
1
0
Table 6-7. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Description
SIGN_FREE (Signature Free Run).
0: Disable. (Default) If this bit was previously set to 1, the signature process stops at the end of the current frame (i.e., at
1: Enable. If SIGN_EN (bit 0) = 1, the signature register captures data continuously across multiple frames.
Reserved.
SIGN_EN (Signature Enable).
0: Disable. (Default) The SIG_VALUE (bits [31:8]) is reset to 000001h and held (no capture).
1: Enable. The next falling edge of VSYNC is counted as the start of the frame to be used for CRC checking with each pixel
After a signature capture, the SIG_VALUE can be read to determine the CRC check status. SIGN_EN can then be reset to
initialize the SIG_VALUE as an essential preparation for the next round of CRC check.
Reserved.
REV_ID (Revision ID). See device errata for value.
DEV_ID (Device ID). See device errata for value.
Reserved.
ALPHA3_WIN_PRIORITY (Alpha Window 3 Priority). Determines the priority of Alpha Window 3. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority (default).
01: Medium priority.
10: Highest priority.
11: Illegal.
Note:
ALPHA2_WIN_PRIORITY (Alpha Window 2 Priority). Determines the priority of Alpha Window 2. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority (default).
01: Medium priority.
10: Highest priority.
11: Illegal.
Note:
ALPHA1_WIN_PRIORITY (Alpha Window 1 Priority). Determines the priority of Alpha Window 1. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority (default).
01: Medium priority.
10: Highest priority.
11: Illegal.
Note:
Reserved
GV_SEL (GV Select). Selects input video format.
0: YUV format.
1: RGB format.
Note:
the next falling edge of VSYNC).
clock beginning with the next VSYNC.
If SIGN_FREE (bit 2) = 1, the signature register captures the pixel data signature continuously across multiple frames.
If SIGN_FREE (bit 2) = 0, a signature is captured for one frame at a time, starting from the next falling VSYNC.
Priority of enabled alpha windows must be different.
Priority of enabled alpha windows must be different.
Priority of enabled alpha windows must be different.
Mixing and blending configurations are created using bits [13, 11:9] of this register. See Table 6-1 "Valid Mix-
ing/Blending Configurations" on page 327.
If this bit is set to 1, EN_42X (F4BAR0+Memory Offset 00h[28]) must be programmed to 0.
Video De-Interlacing and Alpha Control Register (R/W)
(Continued)
Device and Revision Identification (RO)
345
Reset Value: 0000xxxxh
Reset Value: 00060000h
www.national.com

Related parts for SC2200