SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 204

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Index 45h
Index 46h
Index 47h
Index 48h-4Bh
Index 4Ch-4Fh
Index 50h
31:0
7:6
7:3
Bit
0
5
4
3
2
1
0
2
1
0
7
6
5
Description
X-Bus Warm Start. Writing and reading this bit each have different meanings.
When reading this bit, it indicates whether or not a warm start occurred since power-up:
0: A warm start occurred.
1: No warm start has occurred.
When writing this bit, it can be used to trigger a system-wide reset:
0: No effect.
1: Execute system-wide reset (used only for clock configuration at power-up).
Reserved. Resets to 11.
F5 (PCI Function 5). When asserted (set to 1), enables the register space designated as F5.
This bit must always be set to 1. (Default)
F4 (PCI Function 4). When asserted (set to 1), enables the register space designated as F4.
This bit must always be set to 1. (Default)
F3 (PCI Function 3). When asserted (set to 1), enables the register space designated as F3.
This bit must always be set to 1. (Default)
F2 (PCI Function 2). When asserted (set to 1), enables the register space designated as F2.
This bit must always be set to 1. (Default)
F1 (PCI Function 1). When asserted (set to 1), enables the register space designated as F1.
This bit must always be set to 1. (Default)
Reserved. Must be set to 0.
Reserved. Must be set to 0.
F0BAR1 (PCI Function 0, Base Address Register 1). F0BAR1, pointer to I/O mapped LPC configuration registers.
0: Disable.
1: Enable.
F0BAR0 (PCI Function 0, Base Address Register 0). F0BAR0, pointer to I/O mapped GPIO configuration registers.
0: Disable.
1: Enable.
Reserved. Must be set to 0.
Top of System Memory. Highest address in system used to determine active decode for external PCI mastered memory
cycles.
If an external PCI master requests a memory address below the value programmed in this register, the cycle is transferred
from the external PCI bus interface to the Fast-PCI interface for servicing by the GX1 module.
Note:
PIT Software Reset.
0: Disable.
1: Enable.
PIT Counter 1.
0: Forces Counter 1 output (OUT1) to zero.
1: Allows Counter 1 output (OUT1) to pass to the Port 061h[4].
PIT Counter 1 Enable.
0: Sets GATE1 input low.
1: Sets GATE1 input high.
The four least significant bits must be set to 1100.
(Continued)
Miscellaneous Enable Register (R/W)
PCI Functions Enable Register (R/W)
PIT Control/ISA CLK Divider (R/W)
Top of System Memory (R/W)
Reserved
Reserved
204
Reset Value: FFFFFFFFh
Reset Value: FEh
Reset Value: 7Bh
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Revision 3.0